參數(shù)資料
型號: M12L32162A
廠商: Elite Semiconductor Memory Technology Inc.
英文描述: 1M x 16Bit x 2Banks Synchronous DRAM
中文描述: 100萬x 16Bit的X 2Banks同步DRAM
文件頁數(shù): 15/29頁
文件大?。?/td> 719K
代理商: M12L32162A
ES MT
Page Read & Write Cycle at Same Bank @ Burst Length=4
Preliminary
M12L32162A
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Apr. 2007
Revision
:
0.3
15/29
*Note :
1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus
contention.
2.Row precharge will interrupt writing. Last data input, t
RDL
before Row precharge, will be written.
3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
CLOCK
CKE
CS
RAS
CAS
BA
ADDR
A10/AP
CL=2
CL=3
WE
DQM
HIGH
t
RCD
*Note2
Ra
Ca0
Cb0
Cc0
Cd0
Ra
Qa0
Qa1
Qb0
Qb1
Qb2
Dc0
Dc1
Dd0
Dd1
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd2
t
CDL
*Note1
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
DQ
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
t
RDL
*Note3
相關(guān)PDF資料
PDF描述
M12L32162A-7BG 1M x 16Bit x 2Banks Synchronous DRAM
M12L32162A-7TG 1M x 16Bit x 2Banks Synchronous DRAM
M12L64164A-5BG 1M x 16 Bit x 4 Banks Synchronous DRAM
M12L64164A-6BG 1M x 16 Bit x 4 Banks Synchronous DRAM
M12L64164A-7BG 1M x 16 Bit x 4 Banks Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M12L32162A_0712 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16Bit x 2Banks Synchronous DRAM
M12L32162A_09 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16Bit x 2Banks Synchronous DRAM
M12L32162A-5.5BG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16Bit x 2Banks Synchronous DRAM
M12L32162A-5.5TG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16Bit x 2Banks Synchronous DRAM
M12L32162A-6BG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16Bit x 2Banks Synchronous DRAM