參數(shù)資料
型號(hào): M12L32162A-7TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 16Bit x 2Banks Synchronous DRAM
中文描述: 2M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝: 0.400 INCH, LEAD FREE, TSOP2-54
文件頁(yè)數(shù): 5/29頁(yè)
文件大?。?/td> 719K
代理商: M12L32162A-7TG
ES MT
Preliminary
M12L32162A
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Apr. 2007
Revision
:
0.3
5/29
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
C
°
V
IH
(min)/V
IL
(max)=2.0V/0.8V)
Version
-7
Parameter
Symbol
Test Condition
CAS
Latency
Unit Note
Operating Current
(One Bank Active)
I
CC1
Burst Length = 1
t
RC
t
RC
(min), t
CC
t
CC
(min), I
OL
= 0mA
100
mA
1
I
CC2P
CKE
V
IL
(max), t
CC
=15ns
2
mA
Precharge Standby
Current in power-down
mode
I
CC2PS
CKE
V
IL
(max), CLK
V
IL
(max), t
CC
=
2
I
CC2N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
=15ns
Input signals are changed one time during 30ns
25
mA
Precharge Standby
Current in non
power-down mode
I
CC2NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
15
mA
I
CC3P
CKE
V
IL
(max), t
CC
=15ns
10
Active Standby Current
in power-down mode
I
CC3PS
CKE
V
IL
(max), CLK
V
IL
(max), t
CC
=
10
mA
I
CC3N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
=15ns
Input signals are changed one time during 30ns
25
mA
Active Standby Current
in non power-down
mode
(One Bank Active)
I
CC3NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
15
mA
3
120
mA
1
Operating Current
(Burst Mode)
I
CC4
I
OL
= 0Ma, Page Burst
All Band Activated, t
CCD
= t
CCD
(min)
2
120
Refresh Current
I
CC5
t
RC
t
RC
(min)
120
mA
2
Self Refresh Current
I
CC6
CKE
0.2V
1
mA
Note:
1.Measured with outputs open. Addresses are changed only one time during t
CC
(min).
2.Refresh period is 64ms. Addresses are changed only one time during t
CC
(min).
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