參數(shù)資料
型號(hào): M12L32162A-7TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 16Bit x 2Banks Synchronous DRAM
中文描述: 2M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝: 0.400 INCH, LEAD FREE, TSOP2-54
文件頁數(shù): 24/29頁
文件大?。?/td> 719K
代理商: M12L32162A-7TG
ES MT
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
Preliminary
M12L32162A
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Apr. 2007
Revision
:
0.3
24/29
*Note :
1.Both banks should be in idle state prior to entering precharge power down mode.
2.CKE should be set high at least 1CLK+tss prior to Row active command.
3.Can not violate minimum refresh specification. (64ms)
C L O C K
C K E
A D D R
DQ
DQ M
A10/AP
Active
Power-down
Exit
P r e c h a r g e
: D o n ' t c a r e
*Note3
*No t e 2
*N ot e 1
t
S S
Ra
Ra
Qa0
Qa1
Qa2
t
S H Z
Prech arge
Power-Down
Entry
Precharge
Power-Down
Exit
Row Active
Active
Power-down
Entry
Read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Ca
BA
RAS
CAS
CS
W E
t
SS
t
SS
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