參數(shù)資料
型號: M12L2561616A-6TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 4M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: 0.400 INCH, LEAD FREE, TSOP2-54
文件頁數(shù): 40/44頁
文件大?。?/td> 908K
代理商: M12L2561616A-6TG
ES MT
M12L2561616A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.2
Publication Date
:
Aug. 2007
40/44
Self Refresh Entry & Exit Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
C S
R A S
C A S
A D D R
W E
DQ
DQM
A10/AP
BA 0, B A1
S e l f Re f r e s h E n t r y
A u t o R e f r e s h
: D o n ' t c a r e
* No t e 2
*N ot e1
t
S S
* No t e 3
* N ot e4
t
R F C
min
* N ot e6
S e l f R e f r e s h E x i t
Hi-Z
Hi-Z
* Not e5
* No te 7
*Note :
TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum t
RAS
is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5.
CS
starts from high.
6. Minimum t
RFC
is required after CKE going high to complete self refresh exit.
7. 8K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst
refresh.
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