參數(shù)資料
型號: M12L2561616A-6TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 4M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: 0.400 INCH, LEAD FREE, TSOP2-54
文件頁數(shù): 13/44頁
文件大?。?/td> 908K
代理商: M12L2561616A-6TG
ES MT
M12L2561616A
Elite Semiconductor Memory Technology Inc.
Revision
:
1.2
Publication Date
:
Aug. 2007
13/44
COMMANDS
Mode register set command
(CS ,RAS ,CAS ,
WE
= Low)
The M12L2561616A has a mode register that defines how the device operates.
In this command, A0~A12, BA0 and BA1 are the data input pins. After power on, the
mode register set command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state.
During 2CLK following this command, the M12L2561616A cannot accept any
other commands.
Activate command
(CS ,RAS = Low,CAS ,
WE
= High)
The M12L2561616A has four banks, each with 4,096 rows.
This command activates the bank selected by BA1 and BA0 (BS) and a row
address selected by A0 through A12.
This command corresponds to a conventional DRAM’s RAS falling.
Precharge command
(CS ,RAS ,
WE
= Low,CAS = High )
This command begins precharge operation of the bank selected by BA1 and BA0
(BS). When A10 is High, all banks are precharged, regardless of BA1 and BA0.
When A10 is Low, only the bank selected by BA1 and BA0 is precharged.
After this command, the M12L2561616A can’t accept the activate command to
the precharging bank during t
RP
(precharge to activate command period).
This command corresponds to a conventional DRAM’s RAS rising.
CLK
CLK
CKE
CKE
CS
CS
RAS
RAS
WE
WE
BA0,BA1
BA0, BA1
(Bank select)
A10
A10
Add
Add
CAS
CAS
H
H
Row
Row
Fig. 1 Mode register set
command
Fig. 2 Row address strobe and
bank active command
CLK
CKE
CS
RAS
WE
BA0, BA1
(Bank select)
A10
(Precharge select)
Add
CAS
H
Fig. 3 Precharge command
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