參數(shù)資料
型號: M12L128168A-7TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 2M x 16 Bit x 4 Banks Synchronous DRAM
中文描述: 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: 0.400 INCH, LEAD FREE, TSOP2-54
文件頁數(shù): 38/43頁
文件大?。?/td> 804K
代理商: M12L128168A-7TG
ESMT
M12L128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
2.0
Publication Date
:
Oct. 2006
38/43
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page
*Note : 1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by
AC parameter of t
RDL
.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
2. Burst stop is valid at every burst length.
C L O C K
C K E
C S
R A S
C A S
A D D R
W E
DQ
DQ M
A10/AP
A13
A12
RAa
CAa
CAb
RAa
DAa0 DAa1
DAb1
DAb0
DAb2
Row Active
( A-Bank)
W rite
(A- Bank)
Burst Stop
W rite
(A-Bank)
:Don't Care
HIGH
DAa2 DAa3 DAa4
DAb3 DAb4 DAb5
Precharge
(A-Bank)
t
B D L
t
R D L
*Not e 1
1
9
2
10
3
4
5
6
7
8
11
12
13
14
17
15
18
16
19
0
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