- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377800 > M12L128168A-7TG (ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC) 2M x 16 Bit x 4 Banks Synchronous DRAM PDF資料下載
參數(shù)資料
| 型號： | M12L128168A-7TG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2M x 16 Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, LEAD FREE, TSOP2-54 |
| 文件頁數(shù)： | 21/43頁 |
| 文件大?。?/td> | 804K |
| 代理商： | M12L128168A-7TG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁
ESMT
8. Burst Stop & Interrupted by Precharge
1 ) W r i t e B u r s t S t o p ( B L = 8 )
M12L128168A
Elite Semiconductor Memory Technology Inc.
Revision
:
2.0
Publication Date
:
Oct. 2006
21/43
9. MRS
*Note: 1. t
BDL
: 1 CLK ; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
2. Number of valid output data after burst stop : 1,2 for CAS latency = 2,3 respectiviely.
3. Write burst is terminated. t
BDL
determinates the last data write.
4. DQM asserted to prevent corruption of locations D2 and D3.
5. Precharge can be issued here or earlier (satisfying t
RAS
min delay) with DQM.
6. PRE : All banks precharge, if necessary.
MRS can be issued only at all banks precharge state.
CLK
C M D
PRE
*N ot e 4
M R S
AC T
t
R P
2C LK
1) Mo d e R e g is t e r S e t
C L K
C MD
D Q (C L2 )
D Q(C L 3 )
C L K
C MD
D Q M
D Q
D 0
D 1
D 2
D 3
W R
STOP
*N o t e 1
Q0
Q1
Q0
Q1
R D
STO P
* N o t e2
2 ) R e a d B u r s t S t o p ( B L = 4 )
D 5
D 4
C L K
C MD
D Q(C L 3 )
C L K
C MD
D Q M
D Q
D 0
D 1
M a sk M as k
W R
Q0
Q1
R D
PR E
1 ) W r i t e i n t e r r u p t e d b y p r e c h a r g e ( B L = 4 )
2 ) R e a d i n t e r r u p t e d b y p r e c h a r g e ( B L = 4 )
* N o t e 2
P R E
* N o t e4
*N o t e 3
D Q (C L2 )
* N o t e5
Q2
Q1
Q2
Q3
Q0
t
R D L
t
B D L
Q3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M12L128324A-7BG | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A-7TG | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A-6BG | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A-6TG | 1M x 32 Bit x 4 Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M12L128168A-7TG2L | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:ABSOLUTE MAXIMUM RATINGS |
| M12L128168A-7TIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:2M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L128324A | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A_09 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
| M12L128324A_1 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 32 Bit x 4 Banks Synchronous DRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。