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| 型號： | M-ORSO82G52BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 76/123頁 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G52BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
56
IPC2_B1 combines links from channels BA,BB
IPC2_B2 combines links from channels BC,BD
The IPC8 block combines cells from all 8 aligned links and transmits them to the FPGA logic.
Before an IPC can begin reading data from the RXFIFOs and assembling cells, it must rst align all FIFOs in a port
bundle. This is accomplished by handshaking signals between the framer and IPC. The framer indicates to the IPC
that framing has been acquired.The behavior of the IPC is dependent on the AUTO_BUNDLE register bit. If
AUTO_BUNDLE is set for all links in a bundle, the link is brought up when the link is considered good by the fram-
ers. If AUTO_BUNDLE is not set, all links in the bundle must be valid before the link is brought up. The framer does
not start lling the FIFOs, however, until the next A1/A2 SONET signal.
As shown in Figure 41, the FIFOs are not ready to be read by the IPC until 60 s after all links in a code group is
up. This ensures that all cells are aligned coming out of the FIFOs for the code group.
Figure 41. Frame Start-up Timing
The next thing the IPC must do is determine when the reads may begin. Before reading any data from a FIFO, the
FIFO must have a full cell available to be read. This is indicated by each FIFO and is registered by the IPC. The IPC
then makes sure that the cells in a given port are received in the order that they are transmitted
The twin-link IPC2 blocks can be run at 1/4 the of 156 MHz rate (39 MHz) since each block parses cells from only
two-links. A 4:1 MUX is used for each IPC2 block to provide a 40-bit bus at 156 MHz across the boundary.
IPC Receive Cell Mode Timing Core/FPGA
This section contains timing diagrams for major interfaces of this block to the FPGA logic when cells are to be
transferred. Figure 42 shows the cell twin-link mode timing. The number of clock cycles to transfer the cell data
depends on the payload size enabled. Error indications for CELL BIP errors and CELL DROP are also shown.
~60
S
HEAD_OF_FRAME
Data
RX_LINK_GOOD
Receive Frame
A1/A2 Framing Byte
RX_FIFO_EN
Frame = 125
S
Data
Cell Data is Ignored, and FIFOs are Empty Until
First Cell in Frame after RX_FIFO_EN goes High
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