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| 型號(hào)： | M-ORSO82G52BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁(yè)數(shù)： | 113/123頁(yè) |
| 文件大?。?/td> | 2207K |
| 代理商： | M-ORSO82G52BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
9
latching of data from any pad. The combination provides for very low setup requirements and zero hold times for
signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data sig-
nal, and register the signals without explicitly building a demultiplexer with a PFU.
On the output side of each PIO, an output from the PLC array can be routed to each output Flip-Flop, and logic can
be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals
and other functions of two output signals.
The output FF, in combination with output signal multiplexing, is particularly useful for registering address signals to
be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The output buffer signal
can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. In addition, this 3-
state signal can be registered or nonregistered.
The Series 4 I/O logic has been enhanced to include modes for speed uplink and downlink capabilities. These
modes are supported through shift register logic, which divides down incoming data rates or multiplies up outgoing
data rates. This new logic block also supports high-speed DDR mode requirements where data are clocked into
and out of the I/O buffers on both edges of the clock.
The new programmable I/O cell allows designers to select I/Os which meet many new communication standards
permitting the device to hook up directly without any external interface translation. They support traditional FPGA
standards as well as high-speed, single-ended, and differential-pair signaling. Based on a programmable, bank-ori-
ented I/O ring architecture, designs can be implemented using 3.3 V, 2.5 V, 1.8 V, and 1.5 V referenced output lev-
els.
Routing
The abundant routing resources of the Series 4 architecture are organized to route signals individually or as buses
with related control signals. Both local and global signals utilize high-speed buffered and nonbuffered routes. One
PLC segmented (x1), six PLC segmented (x6), and bused half chip (xHL) routes are patterned together to provide
high connectivity with fast software routing times and high-speed system performance.
Eight fully distributed primary clocks are routed on a low-skew, high-speed distribution network and may be
sourced from dedicated I/O pads, PLLs, or the PLC logic. Secondary and edge-clock routing is available for fast
regional clock or control signal routing for both internal regions and on device edges. Secondary clock routing can
be sourced from any I/O pin, PLLs, or the PLC logic.
The improved routing resources offer great exibility in moving signals to and from the logic core. This exibility
translates into an improved capability to route designs at the required speeds when the I/O signals have been
locked to specic pins.
System-Level Features
The Series 4 also provides system-level functionality by means of its MicroProcessor Interface, Embedded System
Bus, quad-port Embedded Block RAMs, universal Programmable Phase-Locked Loops, and the addition of highly
tuned networking specic Phase-Locked Loops. These functional blocks allow for easy glueless system interfacing
and the capability to adjust to varying conditions in today’s high-speed networking systems.
MicroProcessor Interface
The MPI provides a glueless interface between the FPGA and PowerPC microprocessors. Programmable in 8-,
16-, and 32-bit interfaces with optional parity to the Motorola
PowerPC 860 bus, it can be used for conguration
and readback, as well as for FPGA control and monitoring of FPGA status. All MPI transactions utilize the Series 4
Embedded System Bus at 66 MHz performance.
A system-level MicroProcessor Interface (MPI) to the FPGA user-dened logic following conguration, through the
system bus, including access to the Embedded Block RAM and general user-logic, is provided by the MPI. The MPI
supports burst data read and write transfers, allowing short, uneven transmission of data through the interface by
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