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| 型號(hào)： | M-ORSO82G52BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁(yè)數(shù)： | 34/123頁(yè) |
| 文件大?。?/td> | 2207K |
| 代理商： | M-ORSO82G52BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
18
Figure 5. Transmitter Architecture
Receiver Architecture
The receiver section receives high-speed serial data at the external differential CML input pins. These data are fed
to the clock recovery section which generates a recovered clock and retimes the data. Therefore the receive clocks
are asynchronous between channels. The data are then optionally framed, reformatted, aligned and passed to the
FPGA logic in various parallel data formats.
The top level receiver architecture is shown in Figure 5. The main logical blocks in the receive path are:
Receive SERDES and 8:32 DEMUX.
SONET processing logic.
Input Port Controllers (IPCs) which contain the cell processing logic.
Depending on the mode of operation, the FPGA to backplane data path may include or bypass the various logical
blocks.
Figure 6. Receive Architecture Block Diagram
32:8
MUX
SERDES
xck
32
write
state
mach
64 x 34
memory
read_data[33:0]
read_addr
6
TxFIFO
TX Frame Proc
Payload
block
(SPE/TOH)
32
DINxx
tx_link_idle
tx_link_valid
156 MHz domain
77.76 MHz domain
DINxx_FP
A1A2 corr enable,
A1A2 gen enable,
32
B1 err enable
scrambler
disable
(soft reg)
OPC8
tx_data[160:0],
cell_payload
tx_data[160:0]
[159:0]
FPGA
311.04 MHz
8
other links in quad
TCK78x (77.76 MHz clk), TCK156x (156 MHz), TCK39x (39 MHz)
TSYSCLKxx (77.76 MHz)
to other links
SYSCLK156[A1,A2,B1,B2,8]
TOH block,
32
REFCLK_[P,N]
155.52 MHz
scram-
bler
transparent mode
(soft reg)
transparent mode
(soft reg)
sdo_bp or cell_begin_ok
tx_link_idle, tx_link_valid
or
OPC2
or cell_payload[39:0]
2.488
Gbits/s
DLG—Output Link Group
data valid
Cell mode blocks
SERDES
8b
RBC[0:1]
LDOUT
8:32
DeMUX
Fr
amer
FP
DOUTxx[31:0]
(read clock)
RWCKxx (77.76 MHz)
32b
2.488
BIP-8
calculator
Descr
amb
ler
bits
[31:24]
32b
RDI
Monitor
bits[26:24]
Cell
Extr
act,
Link
Header
Detector
16x161
FIFO
write
cntl
FIFO sync
block
wr
33b
FP
161 @ 156M
rx_link_good
OOF
alarm
flag
AIS-L
insert
BIP
err
flag
RDI
error
flag
Fast
frame
enable
FIFO
resync
FIFO
threshold
alarm flag
ctls
to other
channels
on OOF
ctls from
other
channels
other
links
IPC8
rx_data
FIFO
wr, rd
control
24x33
FIFO
*160@156 MHz or
* - 160 bits from eight-links combined
REFCLK[P,N]
(155.52 MHz)
from desc
from other links in quad
RCK78[A,B]
RSYS_CLK_x[1,2] (77.76MHz)
SYSCLK156[A1,A2,B1,B2,8]
from SERDES
AIS-L
Inser
t
Force
AIS-L
insertion
SPE
gen
32
from desc
FP
from
desc
DOUTxx_SPE
DOUTxx_FP
or
IPC2
40@156 MHz
BIP
err cnt
rx_FIFO_rd_en
FP
Gbits/s
SONET
Cell
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