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| 型號(hào)： | M-ORSO82G52BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁(yè)數(shù)： | 24/123頁(yè) |
| 文件大?。?/td> | 2207K |
| 代理商： | M-ORSO82G52BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
12
Embedded Core Overview
The functions in the embedded core portion of the ORSO82G5 device include:
Eight channel 2.7 Gbits/s serializer/deserializer functions with Clock and Data Recovery (CDR).
MicroProcessor Interface (MPI) to the FPGA logic and embedded core logic via the Series 4 system bus
Support for OC-48 and OC-192 (in quad OC-48) formats.
SONET framing, scrambling and SONET Mode channel alignment.
Performance monitoring functions such as Bit Interleaved Parity (BIP-8) generation and checking and Out-Of-
Frame (OOF) and Remote Defect Indication (RDI-L) detection.
Cell Mode cell creation and extraction, idle cell insertion/deletion, destriping and striping functions.
Additionally, there are two independent memory blocks in the core. Each embedded RAM block has a capacity of
4K word by 36 bits.
The ORSO82G5 embedded core contains an eight-channel clock and data recovery macrocell and logical blocks
performing functions such as SONET framing, scrambling/descrambling and cell processing. The eight channels
each operate at up to 2.7 Gbits/s with per channel CDR functionality. The CDR interface enables high-speed asyn-
chronous serial data transfer between system devices. Devices can be on the same PC-board, on separate boards
connected across a backplane, or connected by cables. Figure 2 shows a top level block diagram of the backplane
driver logic in the embedded core (embedded RAM not shown).
Figure 2. Top Level Block Diagram ORSO82G5 Embedded Core
Receive (RX) Path
Transmit (TX) Path
Cell
Processing
Pseudo-
SONET
Processing
MUX/DEMUX
&
SERDES
ORCA 4E04
FPGA
Logic
Configurable
as
8
data
channels
Organized
in
two
four
channel
blocks
(quads)
User
Configurab
le
I/O
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