Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
2
Table of Contents
Introduction ................................................................. 1
Table of Contents ........................................................ 2
Embedded Function Features ..................................... 3
Programmable Features ............................................. 4
Programmable Logic System Features ....................... 6
Description .................................................................. 7
What Is an FPSC? ......................................... 7
FPSC Overview .............................................. 7
FPSC Gate Counting ..................................... 7
FPGA/Embedded Core Interface ................... 7
ispLEVER Development System .................... 7
FPSC Design Kit ............................................ 7
FPGA Logic Overview .................................... 8
PLC Logic ....................................................... 8
Programmable I/O .......................................... 8
Routing ........................................................... 9
System-Level Features .................................. 9
MicroProcessor Interface ............................... 9
System Bus .................................................. 10
Phase-Locked Loops ................................... 10
Embedded Block RAM ................................. 10
Configuration ................................................ 10
ORSO82G5 Overview ............................................... 11
Embedded Core Overview ........................... 12
ORSO82G5 Main Operating Modes-
Overview ................................................ 13
Embedded Core Functional Blocks -
Overview ................................................ 14
Loopback - Overview ................................... 16
FPSC Configuration - Overview ................... 16
ORSO82G5 Embedded Core Detailed Description .. 17
Top Level Description - Transmitter (TX) and
Receiver (RX) Architectures .................. 17
Detailed Description - SERDES Only Mode . 21
SONET Mode Operation -
Detailed Description .............................. 26
SONET Mode Transmit Path ....................... 32
SONET Mode Receive Path ........................ 35
Cell Mode Detailed Description .................... 46
Cell Mode Transmit Path .............................. 49
Cell Mode Receive Path ............................... 53
Cell Extractor................................................. 54
Receive FIFO ............................................... 54
Input Port Controllers ................................... 55
IPC Receive Cell Mode Timing Core/FPGA . 56
Reset Conditions .......................................... 64
Embedded Core Block RAM ........................ 65
Register Maps ........................................................... 68
Types of Registers ....................................... 68
Absolute Maximum Ratings ...................................... 88
Recommended Operating Conditions ....................... 88
SERDES Electrical and Timing Characteristics ........ 88
Pin Information .......................................................... 91
Pin Descriptions ........................................... 91
Power Supplies for ORSO82G5.................... 97
Recommended Power Supply Connections.. 98
Recommended Power Supply Filtering
Scheme .................................................. 98
Package Pinouts ........................................ 100
Package Information ............................................... 117
Package Thermal Characteristics Summary ........... 117
θJA ............................................................. 117
ψ
ψJC ............................................................ 117
θJC ............................................................. 117
θJB ............................................................. 118
FPSC Maximum Junction Temperature ..... 118
Package Coplanarity .................................. 118
Heat Sink Vendors for BGA Packages ....... 119
Package Parasitics ..................................... 120
Package Outline Diagrams ........................ 121
680-Pin PBGAM ......................................... 122
Ordering Information ................................................ 123