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| 型號(hào)： | M-ORSO82G52BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁(yè)數(shù)： | 62/123頁(yè) |
| 文件大?。?/td> | 2207K |
| 代理商： | M-ORSO82G52BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
43
When operating in SONET mode, the entire SONET frame is sent to the FPGA. In multi-channel alignment
mode(s), data from all channels within an alignment group are aligned to the A1A2 framing bytes.
Each SONET frame is 125s. The frame starts with 36 clock cycles (77.76Mhz) of TOH followed by 1044 clock
cycles of SPE, followed by 36 clock cycles of TOH, 1044 cycles of SPE.
The DOUTxx_SPE signal indicates TOH or SPE in the data (low for TOH, high for SPE)
Twin pairs are AA, AB (group A1), AC, AD (group A2), BA, BB (group B1) and BC, BD (group B2)
Figure 28 shows the SONET twin alignment mode timing. The frame pulse and SPE indicators are show for each of
the two channels (AA, AB) in twin alignment.
Figure 28. Receive SONET Mode—Twin Align Mode
Only frame pulse (DOUTxx_FP) and clocks are shown for understanding of quad alignment.
Timing of data and SPE indicators are the same as shown for twin alignment.
Twin groups are A1 - AA and AB, A2 - AC and AD, B1 - BA, and BB and B2 - BC and BD
RSYSCLKA1
DOUTAA[31:0]
DOUTAA_FP
T
TTT
T
S
SS
T
SSSS
S
...
1 cycle
36 cycles TOH
1044 cycles SPE
36 cycles TOH
Start of Frame
125 s
Data
T Represents TOH
S Represents SPE
DOUTxx-SPE is high for SPE, low for TOH
Clocks
RSYSCLKA1 is the read clock used for group A1
RSYSCLKA2 is the read clock used for group A2
RSYSCLKB1 is the read clock used for group B1
RSYSBLKB2 is the read clock used for group B2
36 cycles TOH
T
TTT
T
S
SS
T
SSSS
S
Start of Frame
DOUTAA_SPE
DOUTAB[31:0]
DOUTAB_SPE
DOUTAB_FP
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