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參數(shù)資料
| 型號(hào)： | LXT974QC |
| 英文描述： | LAN Transceiver |
| 中文描述： | 網(wǎng)絡(luò)收發(fā)器 |
| 文件頁數(shù)： | 64/68頁 |
| 文件大?。?/td> | 1177K |
| 代理商： | LXT974QC |
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LXT9784
—
Low-Power Octal PHY
64
Datasheet
Table 50. Register 16 (10 Hex) Status and Control
Bit(s)
Name
Description
Type
1
Bit(s)
Name
Description
R/W
16.15:14
Reserved
Constant
“
0
”
.
RO
16.13
Reserved
Constant
“
0
”
.
RW
16.12
Reserved
Constant
“
0
”
.
RO
16.11
Receive De-Serializer In-
Sync Indication
Indicates status of the 100BASE-TX Receive De-Serializer In-Sync
Indication.
RO
16.10
100BASE-TX Power-
Down
Indicates the power state of 100BASE-TX.
1 = Power-Down.
0 = Normal operation.
RO
16.9
10BASE-T Power-Down
Indicates the power state of 10BASE-T.
1= Power-Down.
0= Normal operation.
RO
16.8
Polarity
Indicates 10BASE-T polarity.
1 = Reverse polarity.
0 = normal polarity.
RO
16.7
Reserved
Must be set to zero during write.
RO
16.6:2
PHY Address
Value determined by ID[1:0] and PHY port number (which of 8)
RO
16.1
Speed
Indicates the Auto-Negotiation result.
1 = 100 Mbps.
0 = 10 Mbps.
RO
16.0
Full Duplex
Indicates the Auto-Negotiation result.
1 = Full Duplex.
0 = Half Duplex.
RO
1. Refer to
Table 42 on page 60
for Type definitions.
Table 51. Register 17 (11 Hex) Special Control
Bit(s)
Name
Description
Type
1
17.15
Scrambler By-pass
Scrambler by-pass control.
1 = By-pass Scrambler.
default 0 = Normal Operation.
RW
P
17.14
By-pass 4B/5B
1= 4 bit to 5 bit encoder by-pass.
default 0 = Normal Operation.
RW
P
17.13
Force Transmit
H-Pattern
1 = Force transmit H-pattern.
default 0 = Normal Operation.
RW
17.12
Force 34 Transmit
Pattern
1 = Force 34 transmit pattern.
default 0 = Normal Operation.
RW
P
17.11
Good Link
1 = 100BASE-TX good link indication forcing to ASD output.
default 0 = Normal operation.
RW
P
17.10
Reserved
Must be set to zero during write
RW
1. Refer to
Table 42 on page 60
for Type definitions.
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| LXT975 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Fast Ethernet 10/100 Quad Transceivers |
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