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參數(shù)資料
| 型號(hào)： | LXT974QC |
| 英文描述： | LAN Transceiver |
| 中文描述： | 網(wǎng)絡(luò)收發(fā)器 |
| 文件頁數(shù)： | 61/68頁 |
| 文件大?。?/td> | 1177K |
| 代理商： | LXT974QC |
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Low-Power Octal PHY
—
LXT9784
Datasheet
61
0.9
Restart Auto-
Negotiation
Restarts the auto-negotiation process and is self cleared after 300 ns
1 = Restart auto-negotiation process.
default 0 = normal operation.
RW
SC
0.8
Duplex Mode
Controls the duplex mode when auto-negotiation is disabled. If the PHY reports that
it only able to operate in one duplex mode (via bits 1.15:11), the value of this bit shall
correspond to the mode which the PHY can operate.
When the PHY is placed in Loopback mode, the behavior of the PHY shall not be
affected by the status of this bit, bit 0.8.
1 = Full Duplex.
default 0 = Half Duplex.
RW
0.7
Collision Test
Force collision in response to the assertion of TXEN.
1 = Force COL.
default 0 = disable Collision signal test.
RW
0.6:0
Reserved
Constant
“
0
”
.
RO
Table 44. Status Register (Register 1) Bit Definitions
Bit(s)
Name
Description
Type
1
1.15
100BASE-T4
Constant 0 = PHY not able to perform 100BASE-T4.
RO
1.14
Reserved
Constant
“
0
”
.
RO
1.13
100BASE-TX Half
Duplex
1 = PHY able to perform half duplex 100BASE-TX
0 = PHY not able to operate in 100BASE-TX
RO
1.12
Reserved
Constant
“
0
”
.
RO
1.11
10 Mbps Half Duplex
1 = PHY able to operate at 10 Mbps in half duplex mode
0 = PHY not able to operate in 10BASE-T
RO
1.10:7
Reserved
Constant
“
0
”
.
RO
1.6
MF Preamble
Suppression
Constant 0 = PHY will not accept management frames with preamble
suppressed.
RO
1.5
Auto-Negotiation
Complete
1 = Auto-Negotiation process completed
default 0 = Auto-Negotiation process has not completed.
RO
1.4
Remote Fault
Constant 0 = no remote fault condition detected
RO
1.3
Reserved
Constant 0
RO
1.2
Link Status
1 = Valid link has been established.
default 0 = Invalid link detected.
RO
LL
SC
1.1
Jabber Detect
This bit has meaning only in 10 Mbps mode.
1 = Jabber condition detected.
default 0 = No jabber condition detected.
RO
LH
SC
1.0
Extended Capability
Constant 1 = Extended register capabilities enabled
RO
1. Refer to
Table 42
for Type definitions.
Table 43. Control Register (Register 0) Bit Definitions (Continued)
Bit(s)
Name
Description
Type
1
1. Refer to
Table 42
for Type definitions.
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