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參數(shù)資料
| 型號(hào)： | LXT974QC |
| 英文描述： | LAN Transceiver |
| 中文描述： | 網(wǎng)絡(luò)收發(fā)器 |
| 文件頁(yè)數(shù)： | 60/68頁(yè) |
| 文件大小： | 1177K |
| 代理商： | LXT974QC |
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LXT9784
—
Low-Power Octal PHY
60
Datasheet
5.0
Register Definitions
The PHY registers can be accessed through the MII management interface.
Table 42
defines the bit type designations used in the following tables.
Table 42. Bit Type Designations
Designator
Definition
SC
Self Cleared
RO
Read Only
P
external Pin affects content
LL
Latch Low
LH
Latch High.
Table 43. Control Register (Register 0) Bit Definitions
Bit(s)
Name
Description
Type
1
0.15
Reset
Sets the status and control register of the PHY to their default states and is self-
clearing. The PHY returns a value of
“
1
”
when this register is read until the reset
process has completed and accepts a read or write transaction.
1 = PHY reset.
default 0 = normal operation.
RW
SC
0.14
Loopback
Enable loopback of transmit data to the receive data path. The PHY receive circuitry
is isolated from the network.
Note that this may cause the de-scrambler to lose synchronization and produce 560
ns of
“
dead time
”
.
1 = Loopback enabled.
default 0 = Loopback disabled (normal operation).
RW
0.13
Speed Selection
Controls speed when auto-negotiation is disabled.
default 1 = 100 MBPS
0 = 10 MBPS
RW
P
0.12
Auto-Negotiation
Enable
Bits 0.13 & 0.8 (Speed Selection and Duplex Mode, respectively) are ignored when
auto-negotiation is enabled.
Bits 4.12:5 (Technology Ability Field) depends on the PHY ability (Register 0) to
define the preferred link configuration.
default 1 = auto-negotiation enable.
0 = auto-negotiation disable.
RW
P
0.11
Power Down
1 = Analog section
only
power-down enabled.
default 0 = Power-down disabled (normal operation).
RW
0.10
Isolate
Allows the PHY to isolate the Media Independent Interface. The PHY doesn't
respond on the both transmit and receive activities.
1 = Logical isolate of internal MII interface.
default 0 = Normal operation.
RW
1. Refer to
Table 42
for Type definitions.
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