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參數(shù)資料
| 型號： | LXT386LE |
| 英文描述： | PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 的PCM收發(fā)器|四|優(yōu)稅PCM-30/E-1 |的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁數(shù)： | 45/80頁 |
| 文件大?。?/td> | 1112K |
| 代理商： | LXT386LE |
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Octal T1/E1/J1 Transceiver
—
LXT384
Datasheet
45
4.0
JTAG Boundary Scan
4.1
Overview
The LXT384 supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy
access to the interface pins for board testing purposes.
In addition to the traditional IEE1149.1 digital boundary scan capabilities, the LXT384 also
includes analog test port capabilities. This feature provides access to the TIP and RING signals in
each channel (transmit and receive). This way, the signal path integrity across the primary winding
of each coupling transformer can be tested.
4.2
Architecture
The basic JTAG architecture of the LXT384 is illustrated in
Figure 15
.
The LXT384 JTAG architecture includes a TAP Test Access Port Controller, data registers and an
instruction register. The following paragraphs describe these blocks in detail.
Table 29. AIS Interrupt Status Register, AISIS (15h)
Bit
1
Name
Function
7-0
AISIS7-AISIS0
These bits are set to
“
1
”
every time a AIS status change has occurred since the last
clear interrupt in transceivers 7-0 respectively.
1. On power-up all the register bits are set to
“
0
”
.
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| LXT6155 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:155 Mbps SDH/SONET/ATM Transceiver |
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