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參數(shù)資料
| 型號： | LXT386LE |
| 英文描述： | PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 的PCM收發(fā)器|四|優(yōu)稅PCM-30/E-1 |的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁數(shù)： | 12/80頁 |
| 文件大?。?/td> | 1112K |
| 代理商： | LXT386LE |
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LXT384
—
Octal T1/E1/J1 Transceiver
12
Datasheet
4
4
5
5
C3
C3
C2
C2
RNEG6
BPV6
RPOS6
RDATA6
DO
DO
DO
DO
Receive Negative Data Output.
Bipolar Violation Detect Output.
Receive Positive Data Output.
Receive Data Output
Bipolar Mode:
In clock recovery mode, these pins act as active High bipolar non return
to zero (NRZ) receive signal outputs. A High signal on RPOS
corresponds to receipt of a positive pulse on RTIP/RRING. A High
signal on RNEG corresponds to receipt of a negative pulse on RTIP/
RRING. These signals are valid on the falling or rising edges of RCLK
depending on the CLKE input.
In Data recovery mode, these pins act as RZ data receiver outputs. The
output polarity is selectable with CLKE (Active High output polarity when
CLKE is High and Active Low Polarity when CLKE is Low).
RPOS and RNEG will go to the high impedance state when the MCLK
pin is Low.
Unipolar Mode:
In uni-polar mode, the LXT384 asserts BPV High if any in-service Line
Code Violation is detected. RDATA acts as the receive data output.
Hardware Mode:
During a LOS condition, RPOS and RNEG will remain active.
Host Mode:
RPOS and RNEG will either remain active or insert AIS into the receive
path. Selection is determined by the RAISEN bit in the GCR register.
6
C1
RCLK6
DO
Receive Clock Output.
Normal Mode:
This pin provides the recovered clock from the signal received at RTIP
and RRING. Under LOS conditions there is a transition from RCLK
signal (derived from the recovered data) to MCLK signal at the RCLK
output.
Data Recovery Mode:
If MCLK is High, the clock recovery circuit is disabled and RPOS and
RNEG are internally connected to an EXOR that is fed to the RCLK
output for external clock recovery applications.
RCLK will be in high impedance state if the MCLK pin is Low.
Table 1. LXT384 Pin Description (Sheet 2 of 12)
Pin #
QFP
Ball #
PBGA
Symbol
I/O
1
Description
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output
S: Power Supply; N.C.: Not Connected.
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相關(guān)代理商/技術(shù)參數(shù) |
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| LXT388LE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
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| LXT441 | 制造商:LVL1 制造商全稱:LVL1 功能描述:Switched 56/DDS Integrated DSU/CSU |
| LXT6155 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:155 Mbps SDH/SONET/ATM Transceiver |
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