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參數(shù)資料
| 型號(hào)： | LXT386LE |
| 英文描述： | PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 的PCM收發(fā)器|四|優(yōu)稅PCM-30/E-1 |的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁(yè)數(shù)： | 15/80頁(yè) |
| 文件大?。?/td> | 1112K |
| 代理商： | LXT386LE |
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Octal T1/E1/J1 Transceiver
—
LXT384
Datasheet
15
13
14
15
16
F3
F2
F1
G3
A3
A2
A1
A0
DI
DI
DI
DI
Protected Monitoring/Address Select Inputs.
Hardware Mode
In hardware mode, these pins are used to select a specific port for non
intrusive monitoring. During protection monitoring receiver 0 inputs are
internally connected to a specific transmit or receive port. Receiver 0
routes the data from the selected port to its data and clock recovery
circuits. The data on the monitor port can be routed to TTIP0/TRING0
by activating the remote loopback for channel 0 (TCLK0 must be active
in order for this operation to take place). In addition, the recovered clock
and data can be observed at the RCLK0/RPOS0/RNEG0 outputs.
If A0, A1, and A2 are Low, the LXT384 is configured as octal line
transceiver without monitoring capability.
Transmitter monitoring is not supported when the respective channel is
set to analog loopback mode.
Host Mode
In non-multiplexed host mode, these pins function as non-multiplexed
address pins.
17
G1
VCCIO0
S
Power (I/O).
18
G4
GNDIO0
S
Ground (I/O).
19
H1
VCC0
S
Power (Core).
20
H4
GND0
S
Ground (Core).
Table 1. LXT384 Pin Description (Sheet 5 of 12)
Pin #
QFP
Ball #
PBGA
Symbol
I/O
1
Description
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output
S: Power Supply; N.C.: Not Connected.
A3
A2
A1
A0
Selection
0
0
0
0
No Protection Monitoring
0
0
0
1
Receiver 1
0
0
1
0
Receiver 2
0
0
1
1
Receiver 3
0
1
0
0
Receiver 4
0
1
0
1
Receiver 5
0
1
1
0
Receiver 6
0
1
1
1
Receiver 7
1
0
0
0
No Protection Monitoring
1
0
0
1
Transmitter 1
1
0
1
0
Transmitter 2
1
0
1
1
Transmitter 3
1
1
0
0
Transmitter 4
1
1
0
1
Transmitter 5
1
1
1
0
Transmitter 6
1
1
1
1
Transmitter 7
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