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參數(shù)資料
| 型號(hào)： | LXT386LE |
| 英文描述： | PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 的PCM收發(fā)器|四|優(yōu)稅PCM-30/E-1 |的CMOS | QFP封裝| 100引腳|塑料 |
| 文件頁(yè)數(shù)： | 13/80頁(yè) |
| 文件大小： | 1112K |
| 代理商： | LXT386LE |
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Octal T1/E1/J1 Transceiver
—
LXT384
Datasheet
13
7
7
8
8
D3
D3
D2
D2
TNEG6
UBS6
TPOS6
TDATA6
DI
DI
DI
DI
Transmit Negative Data Input.
Unipolar/Bipolar Select Input.
Transmit Positive Data Input.
Transmit Data Input.
Bipolar Mode:
TPOS/TNEG are active High NRZ inputs. TPOS indicates the
transmission of a positive pulse whereas TNEG indicates the
transmission of a negative pulse.
Unipolar Mode:
When TNEG/UBS is pulled High for more than 16 consecutive TCLK
clock cycles, unipolar I/O is selected. In unipolar mode, B8ZS/HDB3 or
AMI encoding/decoding is determined by the CODEN pin (hardware
mode) or by the CODEN bit in the GCR register (software mode).
TDATA is the data input in unipolar I/O mode.
9
D1
TCLK6
DI
Transmit Clock Input.
10
E1
MCLK
DI
Master Clock Input. MCLK is an independent, free-running reference
clock. It
’
s frequency should be 1.544 MHz for T1 operation and 2.048
MHz for E1 operation.
This reference clock is used to generate several internal reference
signals:
Timing reference for the integrated clock recovery unit
Timing reference for the integrated digital jitter attenuator
Generation of RCLK signal during a loss of signal condition
Reference clock during a blue alarm transmit all ones condition
Reference timing for the parallel processor wait state generation
logic
If MCLK is High, the PLL clock recovery circuit is disabled. In this mode,
the LXT384 operates as simple data receiver.
If MCLK is Low, the complete receive path is powered down and the
output pins RCLK, RPOS and RNEG are switched to tri-state mode.
MCLK is not required if LXT384 is used as a simple analog front-end
without clock recovery and jitter attenuation.
Note:
Wait state generation via RDY/ACK is not available if MCLK is
not provided.
Table 1. LXT384 Pin Description (Sheet 3 of 12)
Pin #
QFP
Ball #
PBGA
Symbol
I/O
1
Description
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output
S: Power Supply; N.C.: Not Connected.
TPOS
TNEG
Selection
0
0
Space
1
0
Positive Mark
0
1
Negative Mark
1
1
Space
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| LXT6155 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:155 Mbps SDH/SONET/ATM Transceiver |
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