參數(shù)資料
型號(hào)： LTC4253ACGN#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 28/34頁(yè)
文件大?。?/td> 383K
描述： IC HOT SWAP CONTRLR -48V 16-SSOP
標(biāo)準(zhǔn)包裝： 2,500
類型： 熱交換控制器
應(yīng)用： 通用
內(nèi)部開(kāi)關(guān)： 無(wú)
電源電壓： 8.2 V ~ 14.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 帶卷 (TR)
LTC4253/LTC4253A
28
425353aff
For more information www.linear.com/4253
APPLICATIONS INFORMATION
Resetting a Fault Latch
A latched circuit breaker fault of the LTC4253/LTC4253A
has the benefit of a long cooling time. The latched fault can
be reset by pulsing the RESET pin high until the TIMER pin
is pulled below V
TMRL
(1V) as shown in Figure 13b. After
the RESET pulse, SS and GATE ramp up without an initial
timing cycle provided the interlock conditions are satisfied.
Alternative methods of reset include using an external
switch to pulse the UV pin below V
UVLO
 (V
UV
  V
UVHST
 
for the LTC4253A) or the V
IN
 pin below (V
LKO
  V
LKH
).
Pulling the TIMER pin below V
TMRL
and the SS pin to 0V
then simultaneously releasing them also achieves a reset.
An initial timing cycle is generated for reset by pulsing the
UV pin or V
IN
 pin, while no initial timing cycle is generated
for reset by pulsing of the TIMER and SS pins.
Using Reset as an ON/OFF Switch
The asynchronous RESET pin can be used as an ON/OFF
function to cut off supply to the external power modules
or loads controlled by the LTC4253/LTC4253A. Pulling
RESET high will pull GATE, SS, TIMER and SQTIMER
low and the PWRGD signal high. The supply is fully cut
off if the RESET pulse is maintained wide enough to fully
discharge the GATE and SS pins. As long as RESET is
high, GATE, SS, TIMER and SQTIMER are strapped to V
EE
and the supply is cut off. When RESET is released, if the
LTC4253/LTC4253A are in UVLO, UV , OV or V
SENSE
 > V
CB
,
turn-on is delayed until the interlock conditions are met
before recovering as described in the Operation, Interlock
Conditions section. If not, the GATE pin will ramp up in a
soft start cycle without going through an initial cycle as
in Figure 13c.
Analog Current Limit and Fast Current Limit
In Figure 14a, when SENSE exceeds V
ACL
, GATE is regulated
by the analog current limit amplifier loop. When SENSE
drops below V
ACL
, GATE is allowed to pull up. In Figure 14b,
when a severe fault occurs, SENSE exceeds V
FCL
 and GATE
immediately pulls down until the analog current amplifier
establishes control. If the severe fault causes V
OUT
to exceed
V
DRNCL
, the DRAIN pin is clamped at V
DRNCL
. I
DRN
 flows
into the DRAIN pin and is multiplied by?. This extra cur-
rent is added to the TIMER pull-up current of 200礎(chǔ). This
accelerated TIMER current of (200礎(chǔ)???營(yíng)
DRN
) produces
a shorter circuit breaker fault delay. Careful selection of
C
T
, R
D
 and MOSFET helps prevent SOA damage in a low
impedance fault condition.
Soft-Start
If the SS pin is not connected, this pin defaults to a linear
voltage ramp, from 0V to 2.2V in about 300祍 (0V to 1.4V
in about 200祍 for the LTC4253A) at GATE start-up, as
shown in Figure 15a. If a soft-start capacitor, C
SS
, is con-
nected to this SS pin, the soft-start response is modified
from a linear ramp to an RC response (Equation?), as
shown in Figure 15b. This feature allows load current to
slowly ramp-up at GATE start-up. Soft-start is initiated at
time point 3 by a TIMER transition from V
TMRH
 to V
TMRL
 
(time points 1 and 2), by the OV pin falling below the V
OVLO
 
(V
OV
  V
OVHST
 for the LTC4253A) threshold after an OV
condition or by the RESET pin falling < 0.8V after a Reset
condition. When the SS pin is below 0.2V , the analog cur-
rent limit amplifier keeps GATE low. Above 0.2V , GATE is
released and 50礎(chǔ) ramps up the compensation network
and GATE capacitance at time point 4. Meanwhile, the SS
pin voltage continues to ramp up. When GATE reaches
the MOSFETs threshold, the MOSFET begins to conduct.
Due to the MOSFETs high g
m
, the MOSFET current quickly
reaches the soft-start control value of V
ACL
(t) (Equation?).
At time point?, the GATE voltage is controlled by the current
limit amplifier. The soft-start control voltage reaches the
circuit breaker voltage, V
CB
 at time point? and the circuit
breaker TIMER activates. As the load capacitor nears full
charge, load current begins to decline below V
ACL
(t). The
current limit loop shuts off and GATE releases at time
point?. At time point?, SENSE voltage falls below V
CB
 
and TIMER deactivates.
Large values of C
SS
 can cause premature circuit breaker
time-out as V
ACL
(t) may marginally exceed the V
CB
 potential
during the circuit breaker delay. The load capacitor is un-
able to achieve full charge in one GATE start-up cycle. A
more serious side effect of a large C
SS
 value is that SOA
duration may be exceeded during soft-start into a low
impedance load. A soft-start voltage below V
CB
 will not
activate the circuit breaker TIMER.
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