參數(shù)資料
型號(hào)： LTC4253ACGN#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 10/34頁(yè)
文件大?。?/td> 383K
描述： IC HOT SWAP CONTRLR -48V 16-SSOP
標(biāo)準(zhǔn)包裝： 2,500
類型： 熱交換控制器
應(yīng)用： 通用
內(nèi)部開(kāi)關(guān)： 無(wú)
電源電壓： 8.2 V ~ 14.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 帶卷 (TR)
LTC4253/LTC4253A
10
425353aff
For more information www.linear.com/4253
PIN FUNCTIONS
TIMER (Pin 13): Timer Input. Timer is used to generate 
an initial timing delay at start-up, and to delay shutdown
in the event of an output overload (circuit breaker fault).
Timer starts an initial timing cycle when the following
conditions are met: RESET is low, UV is high, OV is low,
V
IN
 clears UVLO, TIMER pin is low, GATE pin is lower
than V
GATEL
, SS < 0.2V , and V
SENSE
 V
EE
 < V
CB
. A pull-up
current of 5礎(chǔ) then charges C
T
, generating a time delay.
If C
T
 charges to V
TMRH
 (4V), the timing cycle terminates.
TIMER quickly pulls low and GATE is activated.
If SENSE exceeds 50mV while GATE is high, a circuit breaker
cycle begins with a 200礎(chǔ) pull-up current charging C
T
. If
DRAIN is approximately 7V (6V for the LTC4253A) dur-
ing this cycle, the timer pull-up has an additional current
of 8 " I
DRN
. If SENSE drops below 50mV before TIMER
reaches 4V , a 5礎(chǔ) pull-down current slowly discharges
the C
T
. In the event that C
T
 eventually integrates up to
the V
TMRH
(4V) threshold, the circuit breaker trips, GATE
quickly pulls low and PWRGD1 pulls high. TIMER latches
high with a 5礎(chǔ) pull-up source. This latched fault may be
cleared by driving RESET high until TIMER is pulled low.
Other ways of clearing the fault include pulling the V
IN
 pin
momentarily below (V
LKO
 V
LKH
), pulling TIMER low with
an external device or pulling UV below 2.925V (2.756V
for the LTC4253A).
SQTIMER (Pin 14): Sequencing Timer Input. The sequenc-
ing timer provides a delay t
SQT
 for the power good sequenc-
ing. This delay is adjusted by connecting an appropriate
capacitor to this pin. If the SQTIMER capacitor is omitted,
the SQTIMER pin ramps from 0V to 4V in about 300祍.
EN3 (Pin 15): Power Good Status Output Three Enable. 
This is a TTL compatible input that is used to control the
PWRGD3 output. When EN3 is driven low, PWRGD3 will
go high. When EN3 is driven high, PWRGD3 will go low
provided PWRGD2 has been active for for more than one
power good sequence delay (t
SQT
). EN3 can be used to
control the power good sequence. This pin is internally
pulled low by a 120礎(chǔ) current source.
PWRGD3 (Pin 16): Power Good Status Output Three. 
Power good sequence starts with PWRGD1 latching active
low. PWRGD3 will latch active low after EN3 goes high
and after one power good sequence delay t
SQT 
provided
by the sequencing timer from the time PWRGD2 goes
low, whichever comes later. PWRGD3 is reset by PWRGD1
going high or EN3 going low. This pin is internally pulled
high by a 50礎(chǔ) current source.
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