參數(shù)資料
型號: LSIFC929
英文描述: LSIFC929 dual channel fibre solutions
中文描述: LSIFC929雙通道光纖解決方案
文件頁數(shù): 69/144頁
文件大?。?/td> 1496K
代理商: LSIFC929
PCI Configuration Registers
5-13
Register: 0x0C
BIST/Header/Latency/Cache Line
Read/Write
BIST
Built-In Self-Test (Read Only)
[31:24]
HdTyp
Header Type (Read Only)
This register identifies the layout of bytes 0x10 through
0x3F in configuration space and also whether or not the
device contains multiple functions. The value of this
register is 0x00.
[23:16]
LatTim
Latency Timer (Read/Write)
The
Latency Timer
register specifies, in units of PCI bus
clocks, the value of the Latency Timer for this PCI bus
master. The LSIFC909 supports this timer. All eight bits
are writable, allowing latency values of 0–255 PCI clocks.
Use the following equation to calculate an optimum
latency value for the LSIFC909:
[15:8]
Latency = 2 + (Burst Size * (typical wait states + 1)).
Values greater than optimum are also acceptable.
Cache
Cache Line Size (Read/Write)
This register specifies the system cache line size in units
of 32-bit words. Setting this bit causes the LSIFC909 to
align to cache line boundaries before allowing any
bursting, except during Memory Moves in which the read
and write addresses are not aligned to a burst size
boundary. For more information on this register, see
Section 5.3.3, “Memory Write and Invalidate Command.”
[7:0]
31
24
23
16
BIST
HdTyp
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
8
7
0
LatTim
Cache
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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