參數(shù)資料
型號(hào): LSIFC929
英文描述: LSIFC929 dual channel fibre solutions
中文描述: LSIFC929雙通道光纖解決方案
文件頁(yè)數(shù): 44/144頁(yè)
文件大?。?/td> 1496K
代理商: LSIFC929
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4-4
Signal Descriptions
AD[63:0]
AC18, Y16,
AB18, AA18,
AC19, Y19,
AB19, AA19,
AC20, AB20,
AC21, AB21,
AC22, AB22,
AC23, AB23,
AA20, AA22,
AA23, Y21,
Y22, Y23, W20,
W21, W22,
W23, V21, V22,
V23, U21, U23,
T20, W3, Y1,
Y2, Y3, AA1,
AA2, AB1, AB2,
AC3, AB3, AC4,
AB4, AA4, AC5,
AB5, Y5, AA9,
AC10, AC11,
AB11, AA11,
AC12, AB12,
AA12, AB13,
AA13, Y13,
AC14, AB14,
AA14, AB15,
AC15
T/S
16 mA
The physical long word
Address and Data
are
multiplexed on the same PCI pins. During the first
clock of a transaction, AD[63:0] contains a
physical byte address. During subsequent clocks,
AD[63:0] contain data. A bus transaction consists
of an address phase followed by one or more
data phases. PCI supports both read and write
bursts. AD[7:0] define the least significant byte,
and AD[63:56] define the most significant byte.
AD[63:32] contain an internal 25
μ
A pull-up.
C_BE[7:0]/
AC16, AA16,
AB16, AC17,
AC2, AA5, Y8,
AC13
T/S
16 mA
Bus
Command and Byte Enables
are
multiplexed on the same PCI pins. During the
address phase of a transaction, C_BE[3:0]/
define the bus command. During the data phase,
C_BE[7:0]/ are used as byte enables. The byte
enables determine which byte lanes carry
meaningful data. C_BE[0]/ applies to the least
significant byte, and C_BE[7]/ to the most
significant byte. Byte enables are active LOW.
C_BE[7:4] contain an internal 25
μ
A pull-up.
IDSEL
AC1
I
N/A
Initialization Device Select
is used as a chip
select in place of the upper 24 address lines
during configuration read and write transactions.
Table 4.1
PCI Interface (Cont.) Signals
Name
BGA Pos
Type
Strength Description
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