參數(shù)資料
型號: LSIFC929
英文描述: LSIFC929 dual channel fibre solutions
中文描述: LSIFC929雙通道光纖解決方案
文件頁數(shù): 65/144頁
文件大?。?/td> 1496K
代理商: LSIFC929
PCI Configuration Registers
5-9
VenID
Vendor ID (Read Only)
The least significant half of this register identifies the
manufacturer of the device. The LSI Logic Vendor ID is
0x1000.
[15:0]
Register: 0x04
Status/Command
Read/Write
The most significant half of the
Status/Command
register is used to
record status information for PCI bus-related events.
Reads to this register behave normally. Writes are slightly different in that
bits can be cleared, but not set. A bit is reset whenever the register is
written, and the data in the corresponding bit location is a one. For
instance, to clear bit 31 and not affect any other bits, write the value
0x8000 to the register.
The least significant half of the
Status/Command
register provides
coarse control over a device’s ability to generate and respond to PCI
cycles. When a zero is written to this register, the LSIFC909 is logically
disconnected from the PCI bus for all accesses except configuration
accesses.
DPE
Detected Parity Error (Read/Write)
This bit will be set by the LSIFC909 whenever it detects
a data parity error, even if parity error handling is
disabled.
31
SSE
Signaled System Error (Read/Write)
This bit is set whenever a device asserts the SERR/
signal.
30
31
30
29
28
27
26
25
24
23
16
DPE
SSE
MA
RTA
R
DevSEL/Tim
DPR
R
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
15
9
8
7
6
5
4
3
2
1
0
R
SERR
R
EPER
R
WIM
R
EBM
EMS
EIOS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
相關(guān)PDF資料
PDF描述
LSIFC929X LSIFC929X dual channel fibre solutions
LSIU160 LSIU160 Ultra160 SCSI host adapter
LSIU40HVD LSIU40HVD PCI to Dual Channel SCSI host adapter user's guide v2.2 8/02
LSIU40SE LSIU40SE Dual Channel PCI to Ultra SCSI host adapter user's guide v2.2 8/02
LSIU80LVD LSIU80LVD Ultra2 LVD SCSI host adapter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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