
LRS1805A
39
16. Design Considerations
1. Power Supply Decoupling
To avoid a bad effect to the system by flash memory and Smartcombo RAM power switching characteristics, each
device should have a 0.1μF ceramic capacitor connected between F-V
CC
and GND, between F-V
PP
and GND and
between S-V
CC
and GND.
Low inductance capacitors should be placed as close as possible to package leads.
2. F-V
PP
Trace on Printed Circuit Boards
Updating the memory contents of flash memories that reside in the target system requires that the printed circuit board
designer pay attention to the F-V
PP
Power Supply trace. Use similar trace widths and layout considerations given to the F-
V
CC
power bus.
3. The Inhibition of Overwrite Operation
Please do not execute reprograming “0” for the bit which has already been programed “0”. Overwrite operation may
generate unerasable bit.
In case of reprograming “0” to the data which has been programed “1”.
Program “0” for the bit in which you want to change data from “1” to “0”.
Program “1” for the bit which has already been programed “0”.
For example, changing data from “1011110110111101” to “1010110110111100”
requires “1110111111111110” programing.
4. Power Supply
Block erase, full chip erase, word write with an invalid F-V
PP
(See Chapter 11. DC Electrical Characteristics) produce
spurious results and should not be attempted.
Device operations at invalid F-V
CC
voltage (See Chapter 11. DC Electrical Characteristics) produce spurious results
and should not be attempted.
17. Related Document Information
(1)
Document No.
Note:
1. International customers should contact their local SHARP or distribution sales offices.
Document Name
FUM00701
LH28F320BF, LH28F640BF Series Appendix
sharp