參數(shù)資料
型號(hào)： LRS1805A
廠商： Sharp Corporation
英文描述： Stacked Chip 64M (x16) Flash Memory + 16M (x16) Smartcombo RAM
中文描述： 堆疊芯片64M號(hào)（x16）的閃存16M內(nèi)存（× 16）Smartcombo內(nèi)存
文件頁(yè)數(shù)： 28/57頁(yè)
文件大?。?/td> 1373K
代理商： LRS1805A
LRS1805A
26
12.6 Reset Operations
(T
A
= -25°C to +85°C, F-V
CC
= 2.7V to 3.3V)
Notes
Min.
Notes:
1. A reset time, t
PHQV
, is required from the later of SR.7 (F-RY/BY) going “1” (High-Z) or F-RST going high until outputs
are valid. See the AC Characteristics - read cycle for t
PHQV
.
2. t
PLPH
is <100ns the device may still reset but this is not guaranteed.
3. Sampled, not 100% tested.
4. If F-RST asserted while a block erase, full chip erase or (page buffer) program operation is not executing, the reset will
complete within 100ns.
5. When the device power-up, holding F-RST low minimum 100ns is required after F-V
CC
has been in predefined range and
also has been in stable there.
AC Waveform for Reset Operation
Symbol
Parameter
Max.
Unit
t
PLPH
F-RST Low to Reset during Read
(F-RST should be low during power-up.)
1, 2, 3
100
ns
t
PLRH
t
VPH
t
VHQV
F-RST Low to Reset during Erase or Program
1, 3, 4
22
μ
s
F-V
CC
2.7V to F-RST High
F-V
CC
2.7V to Output Delay
1, 3, 5
100
ns
3
1
ms
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