參數(shù)資料
型號(hào)： LRS1805A
廠商： Sharp Corporation
英文描述： Stacked Chip 64M (x16) Flash Memory + 16M (x16) Smartcombo RAM
中文描述： 堆疊芯片64M號(hào)（x16）的閃存16M內(nèi)存（× 16）Smartcombo內(nèi)存
文件頁(yè)數(shù)： 30/57頁(yè)
文件大小： 1373K
代理商： LRS1805A
LRS1805A
28
13.3 Write Cycle
(1,2,3,4,5,6,7,8)
(T
A
= -25°C to +85°C, S-V
CC
= 2.7V to 3.1V)
Notes
Min.
Notes:
1. Writing data into lower byte (S-WE controlled)
1) Data can be written by adding Low pulse into S-WE when the address is set while holding S-CE
1
= Low,
S-CE
2
= High, S-LB = Low and S-UB = High.
2) The data on lower byte are latched up into the memory cell during S-WE = Low and S-LB = Low.
2. Witing data into lower byte (S-LB controlled)
1) Data can be written by adding Low pulse into S-LB when the address is set while holding S-CE
1
= Low,
S-CE
2
= High, S-UB = High and S-WE = Low.
2) The data on lower byte are latched up into memory cell during S-WE = Low and S-LB = Low.
3. Writing data into upper byte (S-WE controlled)
1) Data can be written by adding Low pulse into S-WE when the address is set while holding S-CE
1
= Low,
S-CE
2
= High, S-LB = High and S-UB = Low.
2) The data on upper byte are latched up into the memory cell during S-WE = Low and S-UB = Low.
4. Writing data into upper byte (S-UB controlled)
1) Data can be written by adding Low pulse S-UB when the address is set while holding S-CE
1
= Low,
S-CE
2
= High, S-LB = High and S-WE = Low.
2) The data on upper byte are latched up into the memory cell during S-WE = Low and S-UB = Low.
5. Writing data into both byte (S-WE controlled)
1) Data can be written by adding Low pulse into S-WE when the address is set while holding S-CE
1
= Low,
S-CE
2
= High, S-LB = Low and S-UB = Low.
2) The data are latched up into the memory cell during S-WE = Low, S-LB = Low and S-UB = Low.
6. Writing data into both byte (S-LB, S-UB controlled)
1) Data can be written by adding Low pulse into S-LB and S-UB when the address is set while holding S-CE
1
= Low,
S-CE
2
= High and S-WE = Low.
2) The data are latched up into the memory cell during S-WE = Low, S-LB = Low and S-UB = Low
7. Read or write with using both S-LB and S-UB, the timing edge of S-LB and S-UB must be same.
8. While DQ pins are in the output state, the data that is opposite to the output data should not be given.
Symbol
Parameter
Max.
Unit
t
WC
t
CW
t
ASC
t
AHC
t
C1H
t
AW
t
AS
t
WP
t
BW
t
WR
t
DW
t
DH
t
OW
t
WHZ
Write Cycle Time
85
32,000
ns
Chip Enable to End of Write
70
ns
Address Setup to S-CE
1
Low
Address Hold to S-CE
1
High
S-CE
1
High Pulse Width
0
ns
0
ns
30
ns
Address Valid to End of Write
70
ns
Address Setup Time
0
ns
Write Pulse Width
40
ns
Byte Select Time
70
ns
Write Recovery Time
0
ns
Input Data Setup Time
35
ns
Input Data Hold Time
0
ns
S-WE High to Output Active
5
ns
S-WE Low to Output in High-Z
30
ns
sharp
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