Stacked Chip (16M Flash & 4M SRAM)
LRS1331
Data Sheet
7
SR.7 = Write State Machine Status (WSMS)
1 = Ready
0 = Busy
SR.6 = Erase Suspend Status (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = Erase and Clear Block
Lock-Bits Status (
ECBLBS
)
1 = Error in Block Erase, Bank Erase or
Clear Block Lock-Bits
0 = Successful Block Erase, Bank Erase or
Clear Block Lock-Bits
SR.4 = Word/Byte Write and Set Lock-Bit
Status (WBWSLBS)
1 = Error in Word/Byte Write or Set
Block/Permanent Lock-Bit
0 = Successful Word/Byte Write or Set
Block/Permanent Lock-Bit
SR.3 = V
CCW
Status (VCCWS)
1 = V
CCW
LOW Detect, Operation Abort
0 = V
CCW
Okay
SR.2 = Word/Byte Write Suspend Status (WBWSS)
1 = Word/Byte Write Suspended
0 = Word/Byte Write in Progress/Completed
SR.1 = Device Protect Status (DPS)
1 = Block Lock-Bits, Permanent Lock-Bits
and/or F-WP Lock Detected, Operation Abort
0 = Unlock
SR.0 = Reserved for future enhancements (R)
NOTES:
1. Check SR.7 to determine block erase, bank erase, word/byte
write or lock-bit configuration completion. SR.6 - SR.0 are invalid
while SR.7 = 0.
2. If both SR.5 and SR.4 are
‘
1
’
s after a block erase, bank erase or
lock-bit configuration attempt, an improper command sequence
was entered.
3. SR.3 does not provide a continuous indication of F-V
CCW
level.
The WSM interrogates and indicates the F-V
CCW
level only after
block erase, bank erase, word/byte write or lock-bit configuration
command sequences. SR.3 is not guaranteed to report accurate
feedback only when F-V
CCW
≠
F-V
CCWH
.
4. SR.1 does not provide a continuous indication of permanent and
block lock-bit and F-WP values. The WSM interrogates the perma-
nent lock-bit, block lock-bit and F-WP only after block erase, bank
erase, word/byte write or lock-bit configuration command
sequences. It informs the system, depending on the attempted
operation, if the block lock-bit is set, permanent lock-bit is set and/
or F-WP is V
IL
. Reading the block lock and permanent lock confi-
gruation codes after writing the Read Identifier codes command
indicates permanent and block lock-bit status..
5. SR.0 is reserved for future use and should be masked out when
polling the status register.
Table 6. Status Register Definition
WSMS
BESS
ECBLBS
WBWSLBS
VCCWS
WBWSS
DPS
R
7
6
5
4
3
2
1
0