參數(shù)資料
型號(hào): LRS1331
廠商: Sharp Corporation
英文描述: Stacked Chip 16M Flash Memory and 4M SRAM
中文描述: 堆疊1,600閃存芯片和4M的SRAM
文件頁(yè)數(shù): 18/26頁(yè)
文件大?。?/td> 216K
代理商: LRS1331
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
18
Data Sheet
SRAM AC ELECTRICAL CHARACTERISTICS
AC Test Conditions
NOTE:
*Including scope and jig capacitance.
Read Cycle
T
A
= -25
°
C to +85
°
C, V
CC
= 2.7 V to 3.6 V
NOTE:
*Active output to HIGH impedance and HIGH impedance to output active
tests specified for a ±200 mV transition from steady state levels into the test load.
Write Cycle
T
A
= -25
°
C to +85
°
C, V
CC
= 2.7 V to 3.6 V
NOTE:
*Active output to HIGH impedance and HIGH impedance to output active
tests specified for a ±200 mV transition from steady state levels into the test load.
PARAMETER
CONDITION
Input pulse level
0.6 V to 2.2 V
Input rise and fall time
5 ns
Input and Output timing reference level
1.5 V
Output load*
1TTL + C
L
(30 pF)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Read Cycle Time
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
t
OH
t
LZ1
t
LZ2
t
OLZ
t
BLZ
t
HZ1
H
HZ2
t
OHZ
t
BHZ
85
ns
Address Access Time
85
ns
Chip Enable Access Time
S-CE
1
S-CE
2
85
ns
85
ns
Output Enable to Output Valid
45
ns
Output hold from address change
10
ns
S-CE
1
, S-CE
2
LOW to Output Active*
S-CE
1
S-CE
2
10
ns
10
ns
S-OE LOW to Output Active*
5
ns
S-UB or S-LB LOW to Output in HIGH Impedance*
5
ns
S-CE
1
, S-CE
2
HIGH to Output in
HIGH Impedance*
S-CE
1
S-CE
2
0
25
ns
0
25
ns
S-OE HIGH to Output in HIGH Impedance*
0
25
ns
S-UB or S-LB HIGH to Output Active*
0
25
ns
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Write Cycle Time
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
t
WZ
85
ns
Chip Enable to End of Write
70
ns
Address Valid to End of Write
70
ns
Address Setup Time
0
ns
Write Pulse Width
60
ns
Write Recovery Time
0
ns
Input Data Setup Time
35
ns
Input Data Hold Time
0
ns
S-WE HIGH to Output Active*
5
ns
S-WE LOW to Output in HIGH Impedance*
0
25
ns
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