參數(shù)資料
型號: LRS1331
廠商: Sharp Corporation
英文描述: Stacked Chip 16M Flash Memory and 4M SRAM
中文描述: 堆疊1,600閃存芯片和4M的SRAM
文件頁數(shù): 22/26頁
文件大?。?/td> 216K
代理商: LRS1331
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
22
Data Sheet
Figure 11. Write Cycle Timing Diagram (S-UB, S-LB Control)
t
WC
t
AW
t
CW
t
WR
t
WR
t
AS
t
BW
t
DW
t
DH
t
WP
HIGH IMPEDANCE
D
OUT
D
IN
ADDRESS
S-OE
S-CE
1
S-CE
2
S-UB, S-LB
S-WE
Data Valid
NOTES:
1. A write occurs during the overlap of a LOW S-CE
1
, a HIGH S-CE
2
and a LOW S-WE,
A write begins at the latest transition among S-CE
1
going LOW, S-CE
2
going HIGH
and
S-WE going LOW. A write ends at the earliest transition among S-CE
1
going HIGH,
S-CE
2
going LOW and S-WE going HIGH. t
WP
is measured from the beginning of
write to the end of write.
2. t
CW
is measured from the later of S-CE
1
going LOW or S-CE
2
going HIGH to the end
of write.
3. t
BW
is measured from the time of going LOW S-UB or LOW S-LB to the end of write.
4. t
AS
is measured from the address valid to the beginning of write.
5. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends
as S-CE
1
going HIGH, S-CE
2
going LOW or S-WE going HIGH.
1331-11
(NOTE 2)
(NOTE 5)
(NOTE 5)
(NOTE 3)
(NOTE 1)
(NOTE 4)
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參數(shù)描述
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