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參數(shù)資料
| 型號(hào)： | LRS1331 |
| 廠商： | Sharp Corporation |
| 英文描述： | Stacked Chip 16M Flash Memory and 4M SRAM |
| 中文描述： | 堆疊1,600閃存芯片和4M的SRAM |
| 文件頁數(shù)： | 13/26頁 |
| 文件大?。?/td> | 216K |
| 代理商： | LRS1331 |
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Stacked Chip (16M Flash & 4M SRAM)
LRS1331
Data Sheet
13
Write Cycle (F-CE Controlled)
1
T
A
= -25
°
C to +85
°
C, V
CC
= 2.7 V to 3.6 V
NOTES:
1. In system where F-CE defines the pulse width (within a F-WE timing waveform), all setup,
hold, and inactive F-WE times should be measured relative to the F-CE waveform.
2. Refer to the
‘
Flash Memory Command Definition
’
section for valid A
IN
and D
IN
for block erase or word write.
Block Erase and Word Write Performance
T
A
= -25
°
C to +85
°
C, V
CC
= 2.7 V to 3.6 V
NOTES:
1. Reference values at T
A
= +25
°
C and V
CC
= 3.0 V, V
PP
= 3.0 V.
2. Sampled, but not 100% tested.
3. Excludes system-level overhead.
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTES
Write Cycle Time
t
AVAV
t
PHEL
t
WLEL
t
ELEH
t
SHEH
t
VPEH
t
AVEH
t
DVEH
t
EHDX
t
EHAX
t
EHWH
t
EHEL
t
EHRL
t
EHGL
t
QVVL
t
QVSL
90
ns
F-RP HIGH Recovery to F-CE going to LOW
1
μs
F-WE Setup to F-CE going LOW
0
ns
F-CE Pulse Width
60
ns
F-WP V
IH
Setup to F-CE going HIGH
F-V
CCW
Setup to F-CE going HIGH
Address Setup to F-CE going HIGH
100
ns
100
ns
50
ns
Data Setup to F-CE going HIGH
50
ns
2
Data Hold from F-CE HIGH
0
ns
2
Address Hold from F-CE HIGH
0
ns
F-WE Hold from F-CE HIGH
0
ns
F-CE Pulse Width HIGH
20
ns
F-CE HIGH to F-RY/BY going LOW
100
ns
Write Recovery before Read
0
ns
F-V
CCW
Hold from Valid SRD, F-RY/BY HIGH Z
F-WP V
IH
Hold from Valid SRD, F-RY/BY HIGH
0
ns
0
ns
SYMBOL
PARAMETER
V
CCW
= 2.7 V to 3.6 V
MIN.
TYP.
1
UNIT
NOTES
MAX.
2
t
WHQV1
t
EHQV1
Word Write Time 32K-word Block
33
200
μs
3
Word Write Time 4K-word Block
36
200
μs
3
Block Write Time 32K-word Block
1.1
2.4
s
3
Block Write Time 4K-word Block
0.15
0.3
s
3
t
WHQV2
t
EHQV2
Block Erase Time 32K-word Block
1.2
6
s
3
Block Erase Time 4K-word Bock
0.6
5
s
3
Full Chip Erase Time
42
210
s
3
t
WHQV3
t
EHQV3
t
WHQV4
t
EHQV4
t
WHRZ1
t
EHRZ1
t
WHRZ2
t
EHRZ2
Set Lock-Bit Time
27.6
200
μs
3
Clear Block Lock-Bits Time
0.64
5
s
3
Word Write Suspend Latency Time to Read
6.0
15
μs
Erase Suspend Latency Time to Read
16.0
30
μs
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LRS1337 | Stacked Chip 32M Flash Memory and 4M SRAM |
| LRS1338A | Stacked Chip 8M Flash Memory and 2M SRAM |
| LRS1341 | Stacked Chip 16M Flash Memory and 2M SRAM |
| LRS1805A | Stacked Chip 64M (x16) Flash Memory + 16M (x16) Smartcombo RAM |
| LRS250 | LIGHT EMITTING DIODES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LRS1337 | 制造商:Sharp Microelectronics Corporation 功能描述:32M (2MX16) FLASH, 4M (256KX16) SRAM, 3V, CSP72 - Trays |
| LRS1338A | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:Stacked Chip 8M Flash Memory and 2M SRAM |
| LRS1341 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:Stacked Chip 16M Flash Memory and 2M SRAM |
| LRS1342 | 制造商:Sharp Microelectronics Corporation 功能描述:COMBO 1MX16 FLASH + 128KX16 SRAM 2.7V TO 3.6V 72FBGA - Trays |
| LRS1348 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM |
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