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20
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5B
(NEW)
MISC I/O 5: Input or Output
0 The MISC I/O 5 pin is configured as an input.
1 The MISC I/O 5 pin is configured as an output.
A low input on MISC I/O 5 is True
A high input on MISC I/O 5 is True
Level sensitive: MISC I/O 5 State bit (in Status
Register) is set to a 1 if MISC I/O 5 is currently True.
Edge sensitive: MISC I/O 5 State bit (in Status
Register) is set to a 1 if MISC I/O 5 has been True
since the last time the Status Register was read.
The output of the MISC I/O 5 pin will be a logic low
(0V).
The output of the MISC I/O 5 pin will be a logic high
(5V).
The MISC I/O 6 pin is configured as an input.
The MISC I/O 6 pin is configured as an output.
A low input on MISC I/O 6 is True
A high input on MISC I/O 6 is True
Level sensitive: MISC I/O 6 State bit (in Status
Register) is set to a 1 if MISC I/O 6 is currently True.
Edge sensitive: MISC I/O 6 State bit (in Status
Register) is set to a 1 if MISC I/O 6 has been True
since the last time the Status Register was read.
The output of the MISC I/O 6 pin will be a logic low
(0V).
The output of the MISC I/O 6 pin will be a logic high
(5V).
MISC I/O 5: Polarity
(if configured as an input)
0
1
MISC I/O 5: Level/Edge sensitive
(if configured as an input)
0
1
MISC I/O 5: Output State
(if configured as an output)
Power On/USB Suspend Default: Output,
Logic High
0
1
MISC I/O 6: Input or Output
0
1
MISC I/O 6: Polarity
(if configured as an input)
0
1
MISC I/O 6: Level/Edge sensitive
(if configured as an input)
0
1
MISC I/O 6: Output State
(if configured as an output)
Power On/USB Suspend Default: Output,
Logic Low
0
1
TEST MODE SETTINGS
5C
5D
ADC Output Code - MSB
ADC Output Code - LSB
n n n n n n n n Used to force the input to the HDPI Divider to a known
value for digital tests
n n n n n n n n
0 0 Normal Operation
0 1 Bypass AFE, Normal ADC Operation
Bypass AFE, bypass ADC digital correction,
output uncorrected ADC MSB
Bypass AFE, bypass ADC digital correction,
output uncorrected ADC LSB
0 0
Normal Operation - ADC Output
0 1
Registers 5C and 5D
1 0
16 bit counter, reset at the start of every scan
1 1
16 bit counter, reset at the start of every line
0 0
Increments by 1
0 1
Increments by 4
1 0
Increments by 16
1 1
N/A
0
Rising
1
Falling
0
Normal Operation
1
CDS signal is output on LAMP
B
pin
0 0 0 0 0 0 0 0 Write 00 to these registers
1 0 0 100 = LM9832 (011 = LM9831, 010 = LM9830)
0 0 0 0 0 0 0 0 Write 00 to these registers
5E
ADC Test Mode
1 0
1 1
Pixel Processing Input Select
16 bit Counter Increment Select
(16 bit counter starts at 0, increments every
datapixel)
MCLK edge for AFE (Set this bit to 0)
CDS Signal
5F-68
69
6A-7F
Reserved
Version Number
Reserved
Address
Function
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Value
LM9832 Register Listing
(Continued)
L