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參數(shù)資料
| 型號： | LM9617CCEA-2 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CQCC48 |
| 封裝： | LCC-48 |
| 文件頁數(shù)： | 19/40頁 |
| 文件大小： | 408K |
| 代理商： | LM9617CCEA-2 |
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Register Set (continued)
Register Name Hclk Generator Register
Address
05 Hex
Mnemonic
VCLKGEN
Type
Read/Write
Reset Value
04 Hex.
Register Name Digital Video Mode 0
Address
06 Hex
Mnemonic
VMODE0
Type
Read/Write
Reset Value
00 Hex
Register Name Digital Video Mode 1
Address
07 Hex
Mnemonic
VMODE1
Type
Read/Write
Reset Value
00 Hext
Register Name Digital Video Mode 2
Address
08 Hex
Mnemonic
VMODE2
Type
Read/Write
Reset Value
00 Hex
Bit
Bit Symbol
Description
7:0
HclkGen
Use to divide the frequency of
the sensors master clock input,
mclk to generate the internal
sensor clock, Hclk.
Program 00 Hex (the default) for
Hclk to equal mclk or divide
mclk by any number between 1
and FF Hex.
Bit
Bit Symbol
Description
7:6
PixDataSel
Use to program the number of
active bits on the digital video bus
d[11:0], starting from the MSB
(d[11]). Inactive bits are tri-stated.:
5:4
PixDataMsb
Use to program the routing of the
MSB output of the internal video
A/D to a bit on the digital video
bus.
3:0
Reserved
00
12 bit mode, bits
d[11:0] of the digital
video bus are active.
This is the default.
01
10 bit mode, bits
d[11:2] of the digital
video bus are active.
10
8 bit mode, bits
d[11:4] of the digital
video bus are active.
11
Reserved.
00
A/D [11:0] -> d[11:0].
01
A/D [10:0] -> d[11:1]
10
A/D [9:0] -> d[11:2]
11
A/D [8:0] -> d[11:3]
Bit
Bit Symbol
Description
7
PixClkMode
Assert to set the pclk to “data
ready mode”. Clear, the default, to
set pclk to “free running mode”.
6
VsyncMode
Assert to set the vsync pin to
“pulse mode”. Clear (the default)
to set the vsync signal to “l(fā)evel
mode”.
5
HsyncMode
Assert to force the hsync signal to
pulse for a minimum of four pixel
clocks at the end of each row.
Clear (the default) to force the
hsync signal to a level indicating
valid data within a row.
4
PixClkPol
Assert to set the active edge of
the pixel clock to negative. Clear
(the default) to set the active edge
of the clock to positive.
3
VsynPol
Assert to force the vsync signal to
generate a logic 0 during a frame
readout (Level Mode), or a nega-
tive pulse at the end of a frame
readout (Pulse Mode). Clear (the
default) to force the vsync signal
to generate a logic 1 during a
frame readout (Level Mode), or a
negative pulse at the end of a
frame readout (Pulse Mode).
2
HsynPol
Assert to force the hsync signal to
generate a logic 0 during a row
readout (Level Mode), or a nega-
tive pulse at the end of a row
readout (Pulse Mode). Clear (the
default) to force the hsync signal
to generate a logic 1 during a row
readout (Level Mode), or a nega-
tive pulse at the end of a readout
(Pulse Mode).
1
OddEvenEn
Assert to force the vsync pin to act
as an odd/even field indicator.
Clear (the default) to force the
vsync pin to act as a vertical syn-
chronization signal.
0
TriState
Assert to tri-state all output signals
(data and control) on the digital
video port. Clear (default) to
enable all signals (data and con-
trol) on the digital video port.
Bit
Bit Symbol
Description
7:4
HsyncAdjust
Use to program the leading edge
of hsync to the first valid pixel at
the beginning of each row. This
can be 0-hex to F-hex corre-
sponding to 0 - 15 pixel clocks.
Default 0.
3:0
Reserved
L
M
9
6
1
7
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