參數(shù)資料
型號: LM9617CCEA-2
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, CQCC48
封裝: LCC-48
文件頁數(shù): 18/40頁
文件大?。?/td> 408K
代理商: LM9617CCEA-2
Confidential
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Register Set
The following section describes all available registers in the
LM9617 register bank and their function.
Register Name Device Rev Register
Mnemonic
REV
Address
01 Hex
Type
Read Only.
Register Name Main Configuration 0
Address
02 Hex
Mnemonic
MCFG0
Type:
Read/Write
Reset Value
00 Hex
Register Name Main Configuration 1
Address
03 Hex
Mnemonic
MCFG1
Type
Read/Write
Reset Value
00 Hex
Register Name Power Control Register 1
Address
04 Hex
Mnemonic
PCR
Type
Read/Write
Reset Value
00 Hex
Bit
Bit Symbol
Description
7:0
SiRev
The silicon revision register.
Bit
Bit Symbol
Description
7
PwrUpBusy
(Read Only Bit)
Indicates that power on initializa-
tion is in progress. The sensor is
ready for use when this bit is at
logic 0.
6
PwrDown
Assert to power down the sensor.
Writing a logic 1 to this register bit
has the same effect as taking the
pdwn pin high. Clear (the default)
this bit to power up the sensor.
5
BPCorrection
Assert to enable the bad pixel
detection and correction circuit.
Clear (the default) to switch it off.
4
BlkLComp
Assert to disable the black level
compensation circuit. Clear (the
default) to switch it on.
3
SnapEnable
Assert to enable the external
snapshot pin. Clear (the default)
to disable the external snapshot
pin.
2:0
Reserved
Bit
Bit Symbol
Description
7
ColorMode
Assert when using a mono-
chrome sensor. When this bit is
at a logic 1, Sub-Sampling is set
to 2:1 and every other row is
read out during interlace mode.
Clear (the default) when using a
color sensor. When this bit is at
logic 0, sub-sampling is set to
4:2 and every other row pair is
read out during interlace mode.
6
ScanMode
Assert to set the sensor to inter-
lace readout mode. Clear (the
default) to set the sensor to pro-
gressive scan read out mode.
5
HSubSamEn
Assert to enable horizontal sub-
sampling. Clear (the default) to
disable horizontal sub-sampling.
4
VSubSamEn
Assert to enable vertical sub-
sampling. Clear (the default) to
disable vertical sub-sampling.
3
Reserved
2
SlaveMode
Use to configure the digital
video port’s synchronisation sig-
nal to operate in slave mode. By
default the digital video’s port’s
synchronization signals are con-
figured to operate in master
mode.
1:0
Reserved
Bit
Bit Symbol
Description
7
ByPassGain
Assert to route the analog video
signal from the output of the CDS
to the input of the 12 bit A/D. Clear
(the default) to route the signal to
the video gain amplifier.
6:4
Reserved
3
PwdnPGA
Assert to power down the pro-
grammable video gain amplifier.
Clear (the default) to power up the
video gain amplifiers.
2:1
Reserved
0
PwDnADC
Assert to power down the 12 bit
analog to digital convertor. Clear
(the default) to power up the 12 bit
analog to digital convertor.
L
M
9
6
1
7
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