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參數(shù)資料
| 型號： | LH543611 |
| 廠商： | Sharp Corporation |
| 英文描述： | 512 x 36 x 2 / 1024 x 36 x 2 Synchronous Bidirectional FIFO |
| 中文描述： | 512 × 36 x一千○二十四分之二× 36 × 2同步雙向先進先出 |
| 文件頁數(shù)： | 21/57頁 |
| 文件大?。?/td> | 475K |
| 代理商： | LH543611 |
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PORT
COMMAND
REGISTER
BITS
CODE
VALUE
AFTER
RESET
FLAG
AFFECTED,
IF ANY
DESCRIPTION
NOTES
A, B
00
L
H
PF
A
, PF
B
EVEN parity in effect.
A correct 9-bit byte has an even
number of ones.
A correct 9-bit byte has an odd number
of ones.
No overwriting of parity bits.
Parity bit over eight least-significant bits
of each byte is overwritten into the
most-significant bit of that byte.
PF
A
is subject to transient glitches
while data bus is changing.
PF
A
is subject to transient glitches
while data bus is changing.
Asynchronous flag clocking.
Synchronous flag clocking.
Asynchronous flag clocking.
Synchronous flag clocking.
Asynchronous flag clocking.
Synchronous flag clocking by
Port B clock.
Synchronous flag clocking by
Port A clock.
Asynchronous flag clocking.
Synchronous flag clocking.
Asynchronous flag clocking.
Synchronous flag clocking.
Full-word parity-error indication
regardless of WS
1
– WS
0
setting.
Full-word, half word, or single-byte
parity-error indication according to
WS
1
– WS
0
setting.
No overwriting of parity bits.
Parity bit over eight least-significant bits
of each byte is overwritten into the
most-significant bit of that byte.
PF
B
is subject to transient glitches
while data bus is changing.
PF
B
remains steady until its value
should change.
Asynchronous flag clocking.
Synchronous flag clocking.
Asynchronous flag clocking.
Synchronous flag clocking.
Asynchronous flag clocking.
Synchronous flag clocking by Port A
clock.
Synchronous flag clocking by Port B
clock.
H
ODD parity in effect.
A
01
L
L
–
Disable Port A parity generation.
H
Enable Port A parity generation.
02
L
L
PF
A
Port A parity-error flag operates
’flowthrough.’
Port A parity-error flag is latched
by CK
A
.
Set by
↑
CK
A
, reset by
↑
CK
B
.
Set and reset by
↑
CK
A
.
Set by
↑
CK
A
, reset by
↑
CK
B
.
Set and reset by
↑
CK
B
.
Set by
↑
CK
A
, reset by
↑
CK
B
.
H
03
L
H
L
H
LL
L
EF
2
04
L
AE
2
05, 06
LL
HF
1
LH
Set and reset by
↑
CK
B
.
HL, HH
Set and reset by
↑
CK
A
.
07
L
H
L
H
L
AF
1
Set by
↑
CK
A
, reset by
↑
CK
B
.
Set and reset by
↑
CKA.
Set by
↑
CK
A
, reset by
↑
CK
B
.
Set and reset by
↑
CK
A
.
Parity check computed over all
four bytes of each word.
Parity check computed over half-
word or single-byte according to
WS
1
– WS
0
setting.
Disable Port B parity generation.
08
L
FF
1
B
09
L
L
PF
B
H
10
L
L
–
H
Enable Port B parity generation.
11
L
L
PF
B
Port B parity-error flag operates
’flowthrough’.
Port B parity-error flag is latched
by CK
B
.
Set by
↑
CKB, reset by
↑
CK
A
.
Set and reset by
↑
CKB.
Set by
↑
CK
B
, reset by
↑
CK
A
.
Set and reset by
↑
CK
A
.
Set and reset by
↑
CK
A
.
H
12
L
H
L
H
LL
L
EF
1
13
L
AE
1
14, 15
LL
HF
2
LH
Set and reset by
↑
CK
A
.
HL, HH
Set and reset by
↑
CK
A
.
Table 5. Control-Register Format
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
21
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|---|---|
| LH543620 | 1024 x 36 Synchronous FIFO |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH543611M-18 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Synchronous Bidirectional FIFO |
| LH543611M-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Synchronous Bidirectional FIFO |
| LH543611M-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Synchronous Bidirectional FIFO |
| LH543611M-30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Synchronous Bidirectional FIFO |
| LH543611M-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Synchronous Bidirectional FIFO |
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