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參數(shù)資料
| 型號： | LH543611 |
| 廠商： | Sharp Corporation |
| 英文描述： | 512 x 36 x 2 / 1024 x 36 x 2 Synchronous Bidirectional FIFO |
| 中文描述： | 512 × 36 x一千○二十四分之二× 36 × 2同步雙向先進(jìn)先出 |
| 文件頁數(shù)： | 14/57頁 |
| 文件大?。?/td> | 475K |
| 代理商： | LH543611 |
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All nine bits of each byte are treated alike by the parity
logic. The byte parity over the nine bits is compared with
the Parity Mode bit in the Control Register, to generate a
byte-parity-error indication. Then, the four byte-parity-
error signals are NORed together, to compute the asser-
tive-LOW parity-flag value. This value may pass through
to the output pin on a flowthrough basis, or it may be
latched, according to the setting of the Control-Register
latching bit for that port (bit 02 or bit 11). (See Figure 6 for
an example of parity checking.)
Parity Generation
Unlike parity checking, parity generation at a port
operates only when it is explicitly invoked by setting the
corresponding Control-Register bit for that port (bit 01 or
bit 10) HIGH. The presumed division of words into bytes
still remains the same as for parity checking. However, it
is no longer true that all nine bits of each byte are treated
alike; now, the most-significant bit of each byte is explicitly
designated as the parity bit for that byte. The parity-gen-
eration process records a new value into that bit position
for each byte passing through the port. (See Figure 6 for
an example of parity generation.)
If the Parity Policy bit (Control Register bit 09), is HIGH,
parity at Port B will be generated for full-words, for half-
words, or for single bytes according to the setting of the
Word-Width Selection control inputs WS
0
and WS
1
. Oth-
erwise, parity will be generated for full-words regardless
of the setting of WS
0
and WS
1
.
The parity bits generated may be even or odd, accord-
ing to the setting of Control-Register bit 00, which is the
same bit that governs their interpretation during parity
checking.
Word-Width Selection and Byte-Order Reversal on
Port B
The word width of data access on Port B is selected
by the WS
0
and WS
1
control inputs. WS
0
and WS
1
both
are tied HIGH for 36-bit access; they both are tied LOW
for single-byte access. For double-byte access, WS
1
is
tied LOW; WS
0
is tied HIGH for straight-through transmis-
sion of 36-bit words, or tied LOW for on-the-fly byte-order
reversal of the four bytes in the word (‘big-endian
little-endian conversion’). (See Table 2a and 2b.)
In the single-byte-access or double-byte-access modes,
FIFO write operations on Port B essentially pack the data to
form 36-bit words, as viewed from Port A. Similarly, single-
byte or double-byte FIFO read operations on Port B essen-
tially unpack 36-bit words through a series of shift
operations. FIFO status flags are updated following the last
access which forms a complete 36-bit transfer.
Since the values for each status flag are computed by
logic directly associated with one of the two FIFO-memory
arrays, and not by logic associated with Port B, the flag
values reflect the array fullness situation in terms of com-
plete 36-bit words and not in terms of bytes or double bytes.
However, there is no such restriction for switching from
writing to reading, or from reading to writing, at Port B. As
long as t
RWS
, t
DS
, and t
A
are satisfied, R/W
B
may change
state after anysingle-byte or double-byte access, and not
only after a full 36-bit-word access.
Also, WS
0
and WS
1
may be changed between full-
words during FIFO operation, without the need for any
reset operation, or for passing any dummy words on
through in advance of real data. If such a change is made
other than at a full-word boundary, however, at least one
dummy word should be used.
Also, the word-width-matching feature continues to
operate properly in ‘loopback’ mode.
Note that the programmable word-width-matching fea-
ture is onlysupported for FIFO accesses. Mailbox and
Data Bypass operations do notsupport word-width
matching between Port A and Port B. Tables 2a and 2b
and Figures 7, 8, and 9, summarize word-width selection
for Port B.
Table 2a. Port B Word-Width Selection
WS
1
WS
0
PORT B DATA WIDTH
H
H
36-Bit
H
L
36-Bit with
Byte-Order Reversal
L
H
18-Bit
L
L
9-Bit
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
14
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| LH543611M-18 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Synchronous Bidirectional FIFO |
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| LH543611M-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Synchronous Bidirectional FIFO |
| LH543611M-30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Synchronous Bidirectional FIFO |
| LH543611M-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Synchronous Bidirectional FIFO |
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