參數(shù)資料
型號(hào)： LH543611
廠商： Sharp Corporation
英文描述： 512 x 36 x 2 / 1024 x 36 x 2 Synchronous Bidirectional FIFO
中文描述： 512 × 36 x一千○二十四分之二× 36 × 2同步雙向先進(jìn)先出
文件頁(yè)數(shù)： 13/57頁(yè)
文件大小： 475K
代理商： LH543611
MBF
2
), which is synchronized to the reading port’s clock.
These New-Mail-Alert Flags are status indicators only,
and cannot inhibit mailbox-register read or write operations.
Request Acknowledge Handshake
A synchronous request-acknowledge handshake fea-
ture is provided for each port, to perform boundary syn-
chronization between asynchronously-operated ports.
The use of this feature is optional. When it is used, the
Request input (REQ
A/B
) is sampled at a rising clock edge.
With REQ
A/B
HIGH, R/W
A/B
determines whether a FIFO
read operation or a FIFO write operation is being re-
quested. The Acknowledge output (ACK
A/B
) is updated
during the following clock cycle(s). ACK
A/B
meets the
setup and hold time requirements of the Enable input
(EN
A
or EN
B
). Therefore, ACK
A/B
may be tied back to the
enable input to directly gate FIFO accesses, at a slight
decrease in maximum operating frequency.
The assertion of ACK
A/B
signifies that REQ
A/B
was
asserted. However, ACK
A/B
does not depend logically on
EN
A/B
; and thus the assertion of ACK
A/B
does not prove
that a FIFO write access or a FIFO read access actually
took place. While REQ
A/B
and EN
A/B
are being held
HIGH, ACK
A/B
may be considered as a synchronous,
predictive boundary flag. That is, ACK
A/B
acts as a
synchronized predictor of the Almost-Full Flag AF for write
operations, or as a synchronized predictor of the Almost-
Empty Flag AE for read operations.
Outside the ‘a(chǎn)lmost-full’ region and the ‘a(chǎn)lmost-empty’
region, ACK
A/B
remains continuously HIGH whenever
REQ
A/B
is held continuously HIGH. Within the ‘a(chǎn)lmost-full’
region or the ‘a(chǎn)lmost-empty’ region, ACK
A/B
occurs only
on every thirdcycle, to prevent an overrun of the FIFO’s
actual full or empty boundaries and to ensure that the t
FWL
(first write latency) and t
FRL
(first read latency) specifica-
tions are satisfied before ACK
A/B
is received.
The ‘a(chǎn)lmost-full region’ is defined as ‘that region, where
the Almost-Full Flag is being asserted’; and the ‘a(chǎn)lmost-
empty region’ as ‘that region, where the Almost-Empty
Flag is being asserted.’ Thus, the extent of these ‘a(chǎn)lmost’
regions depends on how the system has programmed the
offset values for the Almost-Full Flags and the Almost-
Empty Flags. If the system has not programmed them,
then these offset values remain at their default values,
eight in each case.
If a write attempt is unsuccessful because the corre-
sponding FIFO is full, or if a read attempt is unsuccessful
because the corresponding FIFO is empty, ACK
A/B
is not
asserted in response to REQ
A/B
.
If the REQ/ACK handshake is not used, then the
REQ
A/B
input may be used as a second enable input, at
a possible minor loss in maximum operating speed. In this
case, the ACK
A/B
output may be ignored.
WARNING:
Whether or not the REQ/ACK handshake is
being used, the REQ
A/B
input for a port mustbe asserted
for that port to function at all – for FIFO, mailbox, or data-
bypass operation.
Data Retransmit
A retransmit operation resets the read-address pointer of
the corresponding FIFO (#1 or #2) back to the first FIFO
physical memory location, so that data may be reread. The
write pointer is not affected. The status flags are updated;
and a block of up to 512 or 1024 data words, which
previously had been written into and read from a FIFO, can
be retrieved. The block to be retransmitted is bounded by
the first FIFO memory location, and the FIFO memory
location addressed by the write pointer. FIFO #1 retransmit
is initiated by strobing the RT
1
pin LOW. FIFO #2 retransmit
is initiated by strobing the RT
2
pin LOW. Read and write
operations to a FIFO should be stopped while the corre-
sponding Retransmit signal is being asserted.
Parity Checking
The Parity Check Flags, PF
A
and PF
B
, are asserted
(LOW) whenever there is a parity error in the data word
present on the Port A data bus or the Port B data bus
respectively. The inputs to the parity-evaluation logic
come directly (via isolation transistors) from the data-bus
bonding pads in each case. Thus, PF
A
and PF
B
provide
parity-error indications for whatever 36-bit words are
present at Port A and Port B respectively, regardless of
whether those words originated within the LH543611/21
or in the external system.
The four bytes of a 36-bit data word are grouped as
D
0
– D
8
, D
9
–
D
17
, D
18
– D
26
, and D
27
– D
35
. The parity of
each nine-bit byte is individually checked, and the four
single-bit parity indications are logically ORed and inverted
to produce the Parity-Flag output.
If the Parity Policy bit (Control-Register bit 09) is HIGH,
then parity at Port B will be computed over the field
defined by the Word-Width Selection control inputs WS
0
and WS
1
, and then may be for full-words, for half-words,
or for single bytes. Otherwise, parity will be computed
over full-words regardless of the setting of WS
0
and WS
1
.
Parity checking is initialized for odd parity at reset, but
can be reprogrammed for even parity or for odd parity
during operation. Control-Register bit 00 (zero) selects
the parity mode, odd or even. (See Tables 3, 5, and 6, and
Figure 10.)
OPERATIONAL DESCRIPTION (cont’d)
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
13
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