參數(shù)資料
型號(hào): LH543611
廠商: Sharp Corporation
英文描述: 512 x 36 x 2 / 1024 x 36 x 2 Synchronous Bidirectional FIFO
中文描述: 512 × 36 x一千○二十四分之二× 36 × 2同步雙向先進(jìn)先出
文件頁數(shù): 10/57頁
文件大小: 475K
代理商: LH543611
AC ELECTRICAL CHARACTERISTICS
1
(V
CC
= 5 V
±
+10%, T
A
= 0
°
C to 70
°
C)
SYMBOL
DESCRIPTION
–18
–20
–25
–30
–35
UNITS
MIN
18
7
7
7.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
7.5
0.5
5.5
0.5
4
MAX
55
13
9.5
MIN
20
8
8
7.5
0.5
5.5
0.5
5.5
0.5
5.5
0.5
7.5
0.5
5.5
0.5
4
MAX
50
13.8
9.5
MIN
25
10
10
9
0.5
7.5
0.5
7.5
0.5
7.5
0.5
9
0.5
7.5
0.5
4
MAX
40
16
13
MIN
30
12
12
10
0.5
8.5
0.5
8.5
0.5
8.5
0.5
10
0.5
8.5
0.5
4
MAX
33
20
16
MIN
35
15
15
12
0.5
10.5
0.5
10.5
0.5
10.5
0.5
12
0.5
10.5
0.5
4
MAX
28.5
25
18
f
CC
t
CC
t
CH
t
CL
t
DS
t
DH
t
ES
t
EH
t
RWS
t
RWH
t
RQS
t
RQH
t
AS
t
AH
t
WSS
t
WSH
t
A
t
ACK
t
OH
Clock Cycle Frequency
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Read/Write Setup Time
Read/Write Hold Time
Request Setup Time
Request Hold Time
Address Setup Time
2
Address Hold Time
2
Width Select Setup Time
Width Select Hold Time
3
Data Output Access Time
Acknowledge Access Time
Output Hold Time
Output Enable Time, OE LOW to
D
0
– D
35
Low-Z
Output Disable Time, OE HIGH
to D
0
– D
35
High-Z
3
Clock to EF Flag Valid
Clock to FF Flag Valid
Clock to HF Flag Valid
Clock to AE Flag Valid
Clock to AF Flag Valid
Clock to MBF Flag Valid
Data to Parity Flag Valid
4
Reset/Retransmit Pulse Width
5
Reset/Retransmit Setup Time
6
Reset/Retransmit Hold Time
6
Reset LOW to Flag Valid
First Read Latency
7
First Write Latency
8
Bypass Data Setup
Bypass Data Hold
Bypass Data Access
Skew Time Read-to-Write Clock
Skew Time Write-to-Read Clock
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
ZX
1.5
1.5
2
3
3
ns
t
XZ
9
9
12
15
20
ns
t
EF
t
FF
t
HF
t
AE
t
AF
t
MBF
t
PF
t
RS
t
RSS
t
RSH
t
RF
t
FRL
t
FWL
t
BS
t
BH
t
BA
t
SKEW1
t
SKEW2
18
15
7.2
18
18
8.5
2
14
14
14
14
14
14.5
14.5
10
14
21
15.5
20
16
8
20
20
8.5
2
14.5
14.5
14.5
14.5
14.5
15
15
10
14
21
16
25
20
10
25
25
10
3
19
19
19
19
19
19
19
13
17
25
18
30
25
15
30
30
13
4
22
22
22
22
22
22
22
18
20
30
23
35
30
20
35
35
15
5
27
27
27
27
27
27
27
23
25
35
28
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1.
Timing measurements performed at ‘AC Test Condition’ levels.
2.
t
AS
, t
AH
address setup times and hold times need only be satisfied at clock edges which occur while the corresponding enables are being as-
serted.
3.
Values are guaranteed by design; not currently production tested.
4.
Measured with Parity Flag operating in flowthrough mode.
5.
When CK
A
or CK
B
is enabled; t
RS
= t
RSS
+ t
CH
+ t
RSH
.
6.
t
RSS
and/or t
RSH
need not be met unless a rising edge of CK
A
occurs while EN
A
is being asserted, or else a rising edge of CK
B
occurs while
EN
B
is being asserted.
7.
t
FRL
is the minimum first-write-to-first-read delay, following an empty condition, which is required to assure valid read data.
8.
t
FWL
is the minimum first-read-to-first-write delay, following a full condition, which is required to assure successful writing of data.
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
10
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