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參數(shù)資料
| 型號： | LH28F320S3H-L |
| 廠商： | Sharp Corporation |
| 英文描述： | 32 M-bit(4 MB x 8/2 MB x 16)Smart3 Flash Memories(32M位 (4M位 x 8/2M位 x 16) Smart3 技術(shù)閃速存儲器) |
| 中文描述： | 32 M位（4字節(jié)× 8 / 2 MB的× 16）Smart3閃存（32兆位（4分位x 8/2M位× 16）Smart3技術(shù)閃速存儲器） |
| 文件頁數(shù)： | 9/51頁 |
| 文件大?。?/td> | 340K |
| 代理商： | LH28F320S3H-L |
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- 9 -
PRELMNARY
DQ
0
-DQ
15
outputs are placed in a high-impedance
state independent of OE#. If deselected during
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration, the device
continues functioning, and consuming active power
until the operation completes.
LH28F320S3-L/S3H-L
3 BUS OPERATION
The local CPU reads and writes flash memory in-
system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.1
Information can be read from any block, identifier
codes, query structure, or status register
independent of the V
PP
voltage. RP# must be at
V
IH
.
Read
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes,
Query or Read Status Register) to the CUI. Upon
initial device power-up or after exit from deep
power-down mode, the device automatically resets
to read array mode. Five control pins dictate the
data flow in and out of the component : CE#
(CE
0
#, CE
1
#) , OE#, WE#, RP# and WP#. CE
0
#,
CE
1
# and OE# must be driven active to obtain data
at the outputs. CE
0
# and CE
1
# are the device
selection control, and when active enables the
selected memory device. OE# is the data output
(DQ
0
-DQ
15
) control and when active drives the
selected memory data onto the I/O bus. WE# and
RP# must be at V
IH
.
Fig. 15
and
Fig. 16
illustrate a
read cycle.
3.2
With OE# at a logic-high level (V
IH
) , the device
outputs are disabled. Output pins DQ
0
-DQ
15
are
placed in a high-impedance state.
Output Disable
3.3
Either CE
0
# or CE
1
# at a logic-high level (V
IH
)
places the device in standby mode which
substantially reduces device power consumption.
Standby
3.4
RP# at V
IL
initiates the deep power-down mode.
Deep Power-Down
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time t
PHQV
is required
after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.
During block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration modes, RP#-low
will abort the operation. STS remains low until the
reset operation is complete. Memory contents being
altered are no longer valid; the data may be
partially erased or written. Time t
PHWL
is required
after RP# goes to logic-high (V
IH
) before another
command can be written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase, full
chip erase, (multi) word/byte write and block lock-bit
configuration. If a CPU reset occurs with no flash
memory reset, proper CPU initialization may not
occur because the flash memory may be providing
status information instead of array data. SHARP’s
flash memories allow proper CPU initialization
following a system reset through the use of the
RP# input. In this application, RP# is controlled by
the same RESET# signal that resets the system
CPU.
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