
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration operations.
1 INTRODUCTION
This datasheet contains LH28F320S3-L/S3H-L
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F320S3-L/
S3H-L flash memories documentation also includes
ordering information which is referenced in Section 7.
1.1
The LH28F320S3-L/S3H-L are high-performance
32 M-bit Smart 3 flash memories organized as
4 MB x 8/2 MB x 16. The 4 MB of data is arranged
in sixty-four 64 k-byte blocks which are individually
erasable, lockable, and unlockable in-system. The
memory map is shown in
Fig. 1
.
Product Overview
Smart 3 technology provides a choice of V
CC
and
V
PP
combinations, as shown in
Table 1
, to meet
system performance and power expectations. V
PP
at 2.7 V, 3.3 V and 5 V eliminates the need for a
separate 12 V converter. In addition to flexible
erase and program voltages, the dedicated V
PP
pin
gives complete data protection when V
PP
≤
V
PPLK
.
Table 1 V
CC
and V
PP
Voltage Combinations
Offered by Smart 3 Technology
Internal V
CC
and V
PP
detection circuitry auto-
matically configures the device for optimized read
and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and internal
A block erase operation erases one of the device’s
64 k-byte blocks typically within 0.41 second (3.3 V
V
CC
, 5 V V
PP
) independent of other blocks. Each
block can be independently erased 100 000 times
(6.4 million block erases per device). Block erase
suspend mode allows system software to suspend
block erase to read data from, or write data to any
other block.
A word/byte write is performed in byte increments
typically within 12.95 μs (3.3 V V
CC
, 5 V V
PP
). A
multi word/byte write has high speed write
performance of 2.7 μs/byte (3.3 V V
CC
, 5 V V
PP
).
(Multi) word/byte write suspend mode enables the
system to read data from, or write data to any other
flash memory array location.
Individual block locking uses a combination of bits
and WP#, sixty-four block lock-bits, to lock and
unlock blocks. Block lock-bits gate block erase, full
chip erase and (multi) word/byte write operations.
Block lock-bit configuration operations (Set Block
Lock-Bit and Clear Block Lock-Bits commands) set
and cleared block lock-bits.
The status register indicates when the WSM’s block
erase, full chip erase, (multi) word/byte write or
block lock-bit configuration operation is finished.
The STS output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using STS
minimizes both CPU overhead and system power
consumption. STS pin can be configured to
different states using the Configuration command.
The STS pin defaults to RY/BY# operation. When
low, STS indicates that the WSM is performing a
block erase, full chip erase, (multi) word/byte write
or block lock-bit configuration. STS High Z indicates
that the WSM is ready for a new command, block
V
CC
VOLTAGE
2.7 V
3.3 V
V
PP
VOLTAGE
2.7 V, 3.3 V, 5 V
3.3 V, 5 V
LH28F320S3-L/S3H-L
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