參數(shù)資料
型號(hào)： LH28F160S3NS-L13
英文描述： EEPROM|FLASH|1MX16/2MX8|CMOS|SOP|56PIN|PLASTIC
中文描述： 的EEPROM | FLASH動(dòng)畫| 1MX16/2MX8 |的CMOS |專科| 56PIN |塑料
文件頁(yè)數(shù)： 21/56頁(yè)
文件大?。?/td> 373K
代理商： LH28F160S3NS-L13
- 21 -
LH28F160S5-L/S5H-L
and SR.7 will automatically clear and STS will
return to V
OL
. After the (Multi) Word/Byte Write
command is written, the device automatically
outputs status register data when read (see
Fig. 9
).
V
PP
must remain at V
PPH1
(the same V
PP
level
used for (multi) word/byte write) while in (multi)
word/byte write suspend mode. WP# must also
remain at V
IH
or V
IL
.
4.12 Set Block Lock-Bit Command
A flexible block locking and unlocking scheme is
enabled via block lock-bits. The block lock-bits gate
program and erase operations. With WP# = V
IH
,
individual block lock-bits can be set using the Set
Block Lock-Bit command. See
Table 12
for a
summary of hardware and software write protection
options.
Set block lock-bit is executed by a two-cycle
command sequence. The set block lock-bit setup
along with appropriate block or device address is
written followed by either the set block lock-bit
confirm (and an address within the block to be
locked). The WSM then controls the set block lock-
bit algorithm. After the sequence is written, the
device automatically outputs status register data
when read (see
Fig. 10
). The CPU can detect the
completion of the set block lock-bit event by
analyzing the STS pin output or status register bit
SR.7.
When the set block lock-bit operation is complete,
status register bit SR.4 should be checked. If an
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until a new command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally set. An invalid Set Block Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to "1". Also, reliable operations
occur only when V
CC =
V
CC1/2
and V
PP =
V
PPH1
. In
the absence of this high voltage, block lock-bit
contents are protected against alteration.
A successful set block lock-bit operation requires
WP# = V
IH
. If it is attempted with WP# = V
IL
, SR.1
and SR.4 will be set to "1" and the operation will
fail. Set block lock-bit operations with WP# < V
IH
produce spurious results and should not be
attempted.
4.13 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With WP# = V
IH
,
block lock-bits can be cleared using only the Clear
Block Lock-Bits command. See
Table 12
for a
summary of hardware and software write protection
options.
Clear block lock-bits operation is executed by a
two-cycle command sequence. A clear block lock-
bits setup is first written. After the command is
written, the device automatically outputs status
register data when read (see
Fig. 11
). The CPU
can detect completion of the clear block lock-bits
event by analyzing the STS pin output or status
register bit SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bits
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-
Bits command sequence will result in status register
bits SR.4 and SR.5 being set to "1". Also, a reliable
clear block lock-bits operation can only occur when
V
CC =
V
CC1/2
and V
PP =
V
PPH1
. If a clear block lock-
bits operation is attempted while V
PP
≤
V
PPLK
, SR.3
and SR.5 will be set to "1". In the absence of this
high voltage, the block lock-bit contents are
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