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參數(shù)資料
| 型號： | LH28F160BHE-TTL90 |
| 廠商： | Sharp Corporation |
| 英文描述： | 16M (x8/x16) Flash Memory |
| 中文描述： | 1,600（x8/x16）閃存 |
| 文件頁數(shù)： | 27/46頁 |
| 文件大?。?/td> | 679K |
| 代理商： | LH28F160BHE-TTL90 |
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LHF16J04
25
Rev. 1.26
5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory arrays.
SHARP provides three control inputs to accommodate
multiple memory connections. Three-line control provides
for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will not
occur.
To use these control inputs efficiently, an address decoder
should enable CE# while OE# should be connected to all
memory devices and the system’s READ# control line.
This assures that only selected memory devices have
active outputs while deselected memory devices are in
standby mode. RP# should be connected to the system
POWERGOOD signal to prevent unintended writes during
system power transitions. POWERGOOD should also
toggle during system reset.
5.2 RY/BY# and WSM Polling
RY/BY# is an open drain output that should be connected
to V
CC
by a pull up resistor to provides a hardware method
of detecting block erase, full chip erase, word/byte write
and lock-bit configuration completion. It transitions low
after block erase, full chip erase, word/byte write or lock-
bit configuration commands and returns to V
OH
(while
RY/BY# is pull up) when the WSM has finished executing
the internal algorithm.
RY/BY# can be connected to an interrupt input of the
system CPU or controller. It is active at all times. RY/BY#
is also High Z when the device is in block erase suspend
(with word/byte write inactive), word/byte write suspend
or reset modes.
5.3 Power Supply Decoupling
Flash memory power switching characteristics require
careful device decoupling. System designers are interested
in three supply current issues; standby current levels,
active current levels and transient peaks produced by
falling and rising edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’ capacitive and
inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks.
Each device should have a 0.1μF ceramic capacitor
connected between its V
CC
and GND and between its
V
CCW
and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to package
leads. Additionally, for every eight devices, a 4.7μF
electrolytic capacitor should be placed at the array’s power
supply connection between V
CC
and GND. The bulk
capacitor will overcome voltage slumps caused by PC
board trace inductance.
5.4 V
CCW
Trace on Printed Circuit Boards
Updating flash memories that reside in the target system
requires that the printed circuit board designer pay
attention to the V
CCW
Power supply trace. The V
CCW
pin
supplies the memory cell current for word/byte writing
and block erasing. Use similar trace widths and layout
considerations given to the V
CC
power bus. Adequate
V
CCW
supply traces and decoupling will decrease V
CCW
voltage spikes and overshoots.
5.5 V
CC
, V
CCW
, RP# Transitions
Block erase, full chip erase, word/byte write and lock-bit
configuration are not guaranteed if V
CCW
falls outside of a
valid V
CCWH1/2
range, V
CC
falls outside of a valid 2.7V-
3.6V range, or RP#
≠
V
IH
. If V
CCW
error is detected, status
register bit SR.3 is set to "1" along with SR.4 or SR.5,
depending on the attempted operation. If RP# transitions
to V
IL
during block erase, full chip erase, word/byte write
or lock-bit configuration, RY/BY# will remain low until
the reset operation is complete. Then, the operation will
abort and the device will enter reset mode. The aborted
operation may leave data partially altered. Therefore, the
command sequence must be repeated after normal
operation is restored. Device power-off or RP# transitions
to V
IL
clear the status register.
The CUI latches commands issued by system software and
is not altered by V
CCW
or CE# transitions or WSM
actions. Its state is read array mode upon power-up, after
exit from reset mode or after V
CC
transitions below V
LKO
.
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| LH28F160BJE-BTL90 | 16M-BIT(1Mbit x16/2Mbit x8)Boot Block Flash MEMORY(16M位(1M位 x16/2M位 x8)Boot Block 閃速存儲器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH28F160BJB-BTL90 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM |
| LH28F160BJB-TTL90 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM |
| LH28F160BJB-TTLZS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM |
| LH28F160BJE-BTL90 | 功能描述:IC FLASH 16MBIT 90NS 48TSOP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| LH28F160BJE-TTL90 | 制造商:Sharp Microelectronics Corporation 功能描述:NOR Flash Parallel 3.3V 16Mbit 2M/1M x 8bit/16bit 90ns 48-Pin TSOP |
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