參數(shù)資料
型號(hào)： LH28F160BHE-TTL90
廠商： Sharp Corporation
英文描述： 16M (x8/x16) Flash Memory
中文描述： 1,600（x8/x16）閃存
文件頁(yè)數(shù)： 15/46頁(yè)
文件大?。?/td> 679K
代理商： LH28F160BHE-TTL90
LHF16J04
13
Rev. 1.26
4.5 Block Erase Command
Erase is executed one block at a time and initiated by a
two-cycle command. A block erase setup is first written,
followed by an block erase confirm. This command
sequence requires appropriate sequencing and an address
within the block to be erased (erase changes all block data
to FFFFH/FFH). Block preconditioning, erase, and verify
are handled internally by the WSM (invisible to the
system). After the two-cycle block erase sequence is
written, the device automatically outputs status register
data when read (see Figure 5). The CPU can detect block
erase completion by analyzing the output data of the
RY/BY# pin or status register bit SR.7.
When the block erase is complete, status register bit SR.5
should be checked. If a block erase error is detected, the
status register should be cleared before system software
attempts corrective actions. The CUI remains in read
status register mode until a new command is issued.
This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Block Erase command sequence will
result in both status register bits SR.4 and SR.5 being set
to "1". Also, reliable block erasure can only occur when
V
CC
=2.7V-3.6V and V
CCW
=V
CCWH1/2
. In the absence of
this high voltage, block contents are protected against
erasure. If block erase is attempted while V
CCW
≤
V
CCWLK
,
SR.3 and SR.5 will be set to "1". Successful block erase
requires for boot blocks that WP# is V
IH
and the
corresponding block lock-bit be cleared. In parameter and
main blocks case, it must be cleared the corresponding
block lock-bit. If block erase is attempted when the
excepting above conditions, SR.1 and SR.5 will be set to
"1".
4.6 Full Chip Erase Command
This command followed by a confirm command erases all
of the unlocked blocks. A full chip erase setup (30H) is
first written, followed by a full chip erase confirm (D0H).
After a confirm command is written, device erases the all
unlocked blocks block by block. This command sequence
requires appropriate sequencing. Block preconditioning,
erase and verify are handled internally by the WSM
(invisible to the system). After the two-cycle full chip
erase sequence is written, the device automatically outputs
status register data when read (see Figure 6). The CPU can
detect full chip erase completion by analyzing the output
data of the RY/BY# pin or status register bit SR.7.
When the full chip erase is complete, status register bit
SR.5 should be checked. If erase error is detected, the
status register should be cleared before system software
attempts corrective actions. The CUI remains in read
status register mode until a new command is issued. If
error is detected on a block during full chip erase
operation, WSM stops erasing. Full chip erase operation
start from lower address block, finish the higher address
block. Full chip erase can not be suspended.
This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Full Chip Erase command sequence
will result in both status register bits SR.4 and SR.5 being
set to "1". Also, reliable full chip erasure can only occur
when V
CC
=2.7V-3.6V and V
CCW
=V
CCWH1/2
. In the
absence of this high voltage, block contents are protected
against erasure. If full chip erase is attempted while
V
CCW
≤
V
CCWLK
, SR.3 and SR.5 will be set to "1".
Successful full chip erase requires for boot blocks that
WP# is V
IH
and the corresponding block lock-bit be
cleared. In parameter and main blocks case, it must be
cleared the corresponding block lock-bit. If all blocks are
locked, SR.1 and SR.5 will be set to "1".
4.7 Word/Byte Write Command
Word/Byte write is executed by a two-cycle command
sequence. Word/Byte write setup (standard 40H or
alternate 10H) is written, followed by a second write that
specifies the address and data (latched on the rising edge
of WE#). The WSM then takes over, controlling the
word/byte write and write verify algorithms internally.
After the word/byte write sequence is written, the device
automatically outputs status register data when read (see
Figure 7). The CPU can detect the completion of the
word/byte write event by analyzing the RY/BY# pin or
status register bit SR.7.
When word/byte write is complete, status register bit SR.4
should be checked. If word/byte write error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully write
to "0"s. The CUI remains in read status register mode until
it receives another command.
Reliable word/byte writes can only occur when
V
CC
=2.7V-3.6V and V
CCW
=V
CCWH1/2
. In the absence of
this high voltage, memory contents are protected against
word/byte writes. If word/byte write is attempted while
V
CCW
≤
V
CCWLK
, status register bits SR.3 and SR.4 will be
set to "1". Successful word/byte write requires for boot
blocks that WP# is V
IH
and the corresponding block lock-
bit be cleared. In parameter and main blocks case, it must
be cleared the corresponding block lock-bit. If word/byte
write is attempted when the excepting above conditions,
SR.1 and SR.4 will be set to "1".
相關(guān)PDF資料
PDF描述
LH28F160BJE-BTL90 16M-BIT(1Mbit x16/2Mbit x8)Boot Block Flash MEMORY(16M位(1M位 x16/2M位 x8)Boot Block 閃速存儲(chǔ)器)
LH28F160BJE-TTL70 16M-BIT(1Mbit x16/2Mbit x8)Boot Block Flash MEMORY(16M位(1M位 x16/2M位 x8)Boot Block 閃速存儲(chǔ)器)
LH28F160BJHE-BTL70 16M-BIT(1Mbit x16/2Mbit x8)Boot Block Flash MEMORY(16M位(1M位 x16/2M位 x8)Boot Block 閃速存儲(chǔ)器)
LH28F160BJHE-TTL90 16M-BIT ( 1Mbit x16 / 2Mbit x8 )Boot Block Flash MEMORY(16M位( 1M位 x16 / 2M位 x8 )Boot Block 閃速存儲(chǔ)器)
LH28F160BVE-BTL90 16M-BIT(2Mbit x8/1Mbit x16)Boot Block Flash MEMORY(16M位(2M位x8/1M位 x16)Boot Block 閃速存儲(chǔ)器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LH28F160BJB-BTL90 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM
LH28F160BJB-TTL90 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM
LH28F160BJB-TTLZS 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM
LH28F160BJE-BTL90 功能描述:IC FLASH 16MBIT 90NS 48TSOP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤(pán)
LH28F160BJE-TTL90 制造商:Sharp Microelectronics Corporation 功能描述:NOR Flash Parallel 3.3V 16Mbit 2M/1M x 8bit/16bit 90ns 48-Pin TSOP
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*