參數(shù)資料
型號: LH28F160BHE-TTL90
廠商: Sharp Corporation
英文描述: 16M (x8/x16) Flash Memory
中文描述: 1,600(x8/x16)閃存
文件頁數(shù): 13/46頁
文件大?。?/td> 679K
代理商: LH28F160BHE-TTL90
LHF16J04
11
Rev. 1.26
Table 3. Command Definitions
(10)
Bus Cycles
Req’d.
1
2
2
1
2
2
First Bus Cycle
Addr
(2)
X
X
X
X
X
X
Second Bus Cycle
Oper
(1)
Addr
(2)
Command
Notes
Oper
(1)
Write
Write
Write
Write
Write
Write
Data
(3)
FFH
90H
70H
50H
20H
30H
40H or
10H
Data
(3)
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Full Chip Erase
4
Read
Read
IA
X
ID
SRD
5
Write
Write
BA
X
D0H
D0H
Word/Byte Write
2
5,6
Write
X
Write
WA
WD
Block Erase and Word/Byte
Write Suspend
Block Erase and Word/Byte
Write Resume
Set Block Lock-Bit
Clear Block Lock-Bits
Set Permanent Lock-Bit
NOTES:
1. BUS operations are defined in Table 2.1 and Table 2.2.
2. X=Any valid address within the device.
IA=Identifier Code Address: see Figure 4.
BA=Address within the block being erased.
WA=Address of memory location to be written.
3. SRD=Data read from status register. See Table 6 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID=Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock configuration and
permanent lock configuration codes. See Section 4.2 for read identifier code data.
5. If WP# is V
IL
, boot blocks are locked without block lock-bits state. If WP# is V
IH
, boot blocks are locked by block lock-
bits. The parameter and main blocks are locked by block lock-bits without WP# state.
6. Either 40H or 10H are recognized by the WSM as the word/byte write setup.
7. The clear block lock-bits operation simultaneously clears all block lock-bits.
8. If the permanent lock-bit is set, Set Block Lock-Bit and Clear Block Lock-Bits commands can not be done.
9. Once the permanent lock-bit is set, permanent lock-bit reset is unable.
10.Commands other than those shown above are reserved by SHARP for future device implementations and should not be
used.
1
5
Write
X
B0H
1
5
Write
X
D0H
2
2
2
8
Write
Write
Write
X
X
X
60H
60H
60H
Write
Write
Write
BA
X
X
01H
D0H
F1H
7,8
9
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