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參數(shù)資料
| 型號(hào)： | LFX1200B-03F900C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | The ispXPGA architecture |
| 中文描述： | FPGA, 3844 CLBS, 1250000 GATES, PBGA900 |
| 封裝： | FPBGA-900 |
| 文件頁數(shù)： | 18/89頁 |
| 文件大?。?/td> | 941K |
| 代理商： | LFX1200B-03F900C |
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Lattice Semiconductor
ispXPGA Family Data Sheet
18
High Speed Serial Interface Block (sysHSI Block)
The High Speed Serial Interface (sysHSI) allows high speed serial data transfer over a pair of LVDS I/O. The
ispXPGA devices have multiple sysHSI blocks.
Each sysHSI block has two SERDES blocks which contain two main sub-blocks, Transmitter (with a serializer) and
Receiver (with a deserializer) including Clock/Data Recovery Circuit (CDR). Each SERDES can be used as a full
duplex channel. The two SERDES in sysHSI blocks share a common clock and must operate at the same nominal
frequency. Figure 20 shows the sysHSI block.
Device features support two data coding modes: 10B/12B and 8B/10B (for use with other encoding schemes, see
Lattice’s sysHSI technical notes). The encoding and decoding of the 10B/12B standard are performed within the
sysHSI block. For the 8B/10B standard, the symbol boundaries are aligned internally but the encoding and decod-
ing are performed outside the sysHSI block.
Each SERDES block receives a single high speed serial data input stream (with embedded clock) from an input,
and provide a low speed 10-bit wide data stream and a recovered clock to the device. For transmitting, SERDES
converts a 10-bit wide low-speed data stream to a single high-speed data stream with embedded clock for output.
Additionally, multiple sysHSI blocks can be grouped together to form a source synchronous interface of 1-10 chan-
nels.
Table 7 shows the clock sources available for the REFCLKs of the different sysHSI blocks. The Signal Description
table in this data sheet provides the descriptions of the sysHSI block inputs and outputs.
For more information on the SERDES/CDR, refer to Lattice technical note number TN1020,
sysHSI Usage Guide-
lines
.
Figure 20. sysHSI Block Diagram
S
S
M
REFCLK
SOUT
SIN
SS_CLKOUT
SS_CLKIN
SERDES(HSI#A)
Serializer
CAL
CSLOCK
SERDES(HSI#B)
SOUT
SIN
LOSS
TXD
RXD
RECCLK
SYDT
EXLOSS
CDRLOCK
10
10
TXD
RXD
RECCLK
SYDT
LOSS
CDRLOCK
10
10
To PICs
To PICs
To PICs
To PICs
To PICs
From PICs
From PICs
To PICs
To PICs
To PICs
To PICs
To PICs
From PICs
From PICs
From Global
Clock Tree
sysIO
From PICs
To PICs
CDRRST
CDRRST
EXLOSS
From PICs
From PICs
Deserializer and Clock/Data Recovery
CSPLL
Serializer
Deserializer and Clock/Data Recovery
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFX200C-3F900C | The ispXPGA architecture |
| LFX200C-3F900I | The ispXPGA architecture |
| LFX500C-4F900I | The ispXPGA architecture |
| LFX1200C-03F900C | Circular Connector; MIL SPEC:MIL-C-26482, Series I; Body Material:Aluminum Alloy; Series:MS3112; No. of Contacts:19; Connector Shell Size:14; Connecting Termination:Solder; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No |
| LFX1200C-03F900I | The ispXPGA architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFX1200B-03F900I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:The ispXPGA architecture |
| LFX1200B-03FE680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 15376 LUT-4 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFX1200B-03FEN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 1.25M Gt ispJTAG 2. 5/3.3V -3 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFX1200B-03FEN680C2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 15376 LUT-4 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFX1200B-04F900C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 15376 LUT-4 496 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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