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參數(shù)資料
| 型號： | LF3320QC15 |
| 廠商： | LOGIC DEVICES INC |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | Horizontal Digital Image Filter |
| 中文描述： | 12-BIT, DSP-DIGITAL FILTER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 575K |
| 代理商： | LF3320QC15 |
DEVICES INCORPORATED
LF3320
Horizontal Digital Image Filter
2-16
08/16/2000
–
LDS.3320-N
Video Imaging Products
of loading data into Filter B limit
register 7. Data value 3B60H is loaded
as the lower limit and 72A4H is loaded
as the upper limit.
It takes 9S clock cycles to load S
coefficient sets into the device. There-
fore, it takes 2304 clock cycles to load
all 256 coefficient sets. Assuming an
83 MHz clock rate, all 256 coefficient
sets can be updated in less than 27.7 μs,
which is well within vertical blanking
time. It takes 5S clock cycles to load S
round or limit registers. Therefore, it
takes 320 clock cycles to update all
round and limit registers (both Filters A
and B). Assuming an 83 MHz clock
rate, all Filter A and B round/ limit
registers can be updated in 3.84 μs.
ADDR
1
COEF
0
COEF
1
COEFFICIENT SET 1
CLK
LDA/LDB
CFA/CFB
11-0
W1
W1: Coefficient Set 1 written to coefficient banks during this clock cycle.
PAUSEA/PAUSEB
COEF
7
F
IGURE
19. C
OEFFICIENT
B
ANK
L
OADING
S
EQUENCE
WITH
PAUSE I
MPLEMENTATION
The coefficient banks and
Configuration/ Control registers are not
loaded with data until all data values
for the specified address are loaded into
the LF Interface
TM
. In other words, the
coefficient banks are not written to until
all eight coefficients have been loaded
into the LF Interface
TM
. A round register is
not written to until all four data values
are loaded.
F
IGURE
18. C
ONFIGURATION
/C
ONTROL
R
EGISTER
L
OADING
S
EQUENCE
ADDR
1
COEF
0
COEF
7
ADDR
2
COEF
0
COEF
7
ADDR
3
COEF
0
COEF
7
COEFFICIENT SET 1
COEFFICIENT SET 2
COEFFICIENT SET 3
CLK
LDA/LDB
CFA/CFB
11-0
W1
W1: Coefficient Set 1 written to coefficient banks during this clock cycle.
W2: Coefficient Set 2 written to coefficient banks during this clock cycle.
W3: Coefficient Set 3 written to coefficient banks during this clock cycle.
W2
W3
F
IGURE
17. C
OEFFICIENT
B
ANK
L
OADING
S
EQUENCE
ADDR
1
DATA
1
ADDR
3
DATA
4
CONFIG REG
ROUND REGISTER
LIMIT REGISTER
CLK
LDA/LDB
CFA/CFB
11-0
W2
W1: Configuration Register loaded with new data on this rising clock edge.
W2: Select Register loaded with new data on this rising clock edge.
W3: Round Register loaded with new data on this rising clock edge.
W4: Limit Register loaded with new data on this rising clock edge.
W3
W4
DATA
1
DATA
3
DATA
2
ADDR
4
DATA
2
DATA
1
SELECT REG
ADDR
2
DATA
1
W1
DATA
4
DATA
3
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