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參數(shù)資料
| 型號： | LF3320QC15 |
| 廠商： | LOGIC DEVICES INC |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | Horizontal Digital Image Filter |
| 中文描述： | 12-BIT, DSP-DIGITAL FILTER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 575K |
| 代理商： | LF3320QC15 |
DEVICES INCORPORATED
Video Imaging Products
2-15
LF3320
Horizontal Digital Image Filter
08/16/2000
–
LDS.3320-N
There are sixteen limit registers for Filter
A and sixteen for Filter B. Each register
is 32-bits wide and stores both an upper
and lower limit value. The lower limit is
stored in bits 15-0 and the upper limit is
stored in bits 31-16. RSLA
3-0
and
RSLB
3-0
determine which Filter A and B
limit registers respectively are used for
limiting when limiting is enabled.
Configuration and control register
loading is discussed in the LF
Interface
TM
section.
LF Interface
TM
The Filter A and B LF Interfaces
TM
are
used to load data into the Filter A and B
coefficient banks respectively. They are
also used to load data into the configu-
ration and control registers.
The following section describes how
the Filter A LF Interface
TM
works. The
Filter A and B LF Interfaces
TM
are
identical in function. If LDA and
CFA
11-0
are replaced with LDB and
CFB
11-0
, the following section will
describe how the Filter B LF Interface
TM
works.
LDA is used to enable and disable the
Filter A LF Interface
TM
. When LDA goes
LOW, the Filter A LF Interface
TM
is
enabled for data input. The first value
fed into the interface on CFA
11-0
is an
address which determines what the
interface is going to load. The three
most significant bits (CFA
11-9
) deter-
mine if the LF Interface
TM
will load
coefficient banks or
Configuration/ control registers (see
Table 8). The nine least significant bits
(CFA
8-0
) are the address for whatever
is to be loaded (see Tables 9 through
14). For example, to load address 15 of
the Filter A coefficient banks, the first
data value into the LF Interface
TM
should be 00FH. To load Filter A limit
register 10, the first data value should
be C0AH. The first address value
should be loaded into the interface on
the same clock cycle that latches the
HIGH to LOW transition of LDA (see
Figures 17 and 18).
BITS
FUNCTION
DESCRIPTION
0
Cascade Mode
0 : Last In Line
1 : First or Middle in Line
1
Single/Dual Filter Mode
0 : Single Filter Mode
1 : Dual Filter Mode
2
Filter B Input
0 : RIN
11-0
1 : DIN
11-0
3
Output Adder Control
0 : Filter A + Filter B
1 : Filter A + Filter B (Filter B Scaled by 2
-12
)
4
Matrix Multiply Mode
0 : Disabled
1 : Enabled
5
Accumulator Access Mode
0 : Disabled
1 : Enabled
11-6
Reserved
Must be set to
“
0
”
T
ABLE
7.
C
ONFIGURATION
R
EGISTER
5 – A
DDRESS
205H
BITS
FUNCTION
DESCRIPTION
0
Filter B Limit Enable
0 : Limiting Disabled
1 : Limiting Enabled
1
Filter A Limit Enable
0 : Limiting Disabled
1 : Limiting Enabled
11-2
Reserved
Must be set to
“
0
”
T
ABLE
6.
C
ONFIGURATION
R
EGISTER
4 – A
DDRESS
204H
The next value(s) loaded into the
interface are the data value(s) which
will be stored in the bank or register
defined by the address value. When
loading coefficient banks, the interface
will expect eight values to be loaded
into the device after the address value.
The eight values are coefficients 0
through 7. When loading configura-
tion or select registers, the interface
will expect one value after the address
value. When loading round or limit
registers, the interface will expect four
values after the address value. Figures
11 and 12 show the data loading
sequences for the coefficient banks and
Configuration/ control registers.
Both PAUSEA and PAUSEB allow the
user to effectively slow the rate of data
loading through the LF Interface
TM
.
When PAUSEA is HIGH, the LF
Interface
TM
affecting the data used for
Filter A is held until PAUSEA is
returned to a LOW. When PAUSEB is
HIGH, the LF Interface
TM
affecting the data
used for Filter B is held until PAUSEB is
returned to a LOW. Figures 19 through 22
display the effects of both PAUSEA and
PAUSEB while loading coefficient and
control data.
Table 15 shows an example of loading
data into the coefficient banks. The
following data values are written into
address 10 of coefficient banks 0
through 7: 210H, 543H, C76H, 9E3H,
701H, 832H, F20H, 143H. Table 16
shows an example of loading data into
a Configuration Register. Data value
003H is written into Configuration
Register 4. Table 17 shows an example
of loading data into a round register.
Data value 7683F4A2H is written into
Filter A round register 12.
Table 18 shows an example of loading
data into a select register. Data value
00FH is loaded into Filter A select
register 2. Table 19 shows an example
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