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參數(shù)資料
| 型號(hào)： | LF3320QC15 |
| 廠商： | LOGIC DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | Horizontal Digital Image Filter |
| 中文描述： | 12-BIT, DSP-DIGITAL FILTER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁(yè)數(shù)： | 10/24頁(yè) |
| 文件大?。?/td> | 575K |
| 代理商： | LF3320QC15 |
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DEVICES INCORPORATED
LF3320
Horizontal Digital Image Filter
2-10
08/16/2000
–
LDS.3320-N
Video Imaging Products
F
IGURE
13.
I/D R
EGISTER
D
ATA
P
ATHS
ALU
A
B
ALU
A
B
COEF 7
COEF 6
1
1
1
1
D
R
ALU
A
B
ALU
A
B
COEF 7
2
COEF 6
1
1
1
1
D
R
Delay Stage N
–
1
ALU
A
B
ALU
A
B
COEF 6
1
1
1
1
D
R
EVEN-TAP MODE
ODD-TAP MODE
ODD-TAP INTERLEAVE MODE
COEF 7
2
Delay Stage N
F
IGURE
12.
S
YMMETRIC
C
OEFFICIENT
S
ET
E
XAMPLES
1
2
3
4
5
6
7
8
Even-Tap, Even-Symmetric
Coefficient Set
Odd-Tap, Even-Symmetric
Coefficient Set
1
2
3
4
5
6
7
8
Even-Tap, Odd-Symmetric
Coefficient Set
1
2
3
4
5
6
7
The ALUs can perform two operations:
A+B and B–A. Bit 0 of Configuration
Register 0 determines the operation of
the ALUs in Filter A.
Bit 0 of Configuration Register 2 deter-
mines the operation of the ALUs in Filter
B. A+B is used with
symmetric coefficient sets. B–A is used
with odd-symmetric coefficient sets.
even-
Also, either the A or B operand may be
set to 0. Bits 1 and 2 of Configuration
Register 0 and Configuration Register 2
control the ALU inputs in
Filters A and B respectively. A+0 or B+0
are used with asymmetric coefficient
sets.
Interleave/Decimation Registers
The Interleave/Decimation Registers (I/D
Registers) feed the ALU inputs. They
allow the device to filter up to sixteen data
sets interleaved into the same data stream
without having to separate the data sets.
The I/D Registers should be set to a length
equal to the number of data sets inter-
leaved together.
For example, if two data sets are inter-
leaved together, the I/D Registers should
be set to a length of two. Bits 1 through 4 of
Configuration Register 1 and Configura-
tion Register 3 determine the length of the
I/D Registers in Filters A and B respec-
tively.
The I/D Registers also facilitate using
decimation to increase the number of filter
taps. Decimation by N is accomplished by
reading the filter’s output once every N
clock cycles. The device supports decima-
tion up to 16:1. With no decimation, the
maximum number of filter taps is sixteen.
When decimating by N, the number of
filter taps becomes 16N because there are
N–1 clock cycles when the filter’s output is
not being read. The extra clock cycles are
used to calculate more filter taps.
When decimating, the I/ D Registers
should be set to a length equal to the
decimation factor. For example, when
performing a 4:1 decimation, the I/ D
Registers should be set to a length of
four. When decimation is disabled or
when only one data set (non-interleaved
data) is fed into the device, the I/ D
Registers should be set to a length of
one.
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