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參數(shù)資料
| 型號(hào)： | LF3347QC12 |
| 廠商： | LOGIC DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | CAP 1.0UF 63V METAL POLY |
| 中文描述： | 12-BIT, DSP-DIGITAL FILTER, PQFP120 |
| 封裝： | PLASTIC, QFP-120 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大小： | 80K |
| 代理商： | LF3347QC12 |
DEVICES INCORPORATED
Video Imaging Products
LF3347
High-Speed Image Filter with Coefficient RAM
High-Speed Image Filter with Coefficient RAM
08/16/2000–LDS.3347-G
1
K
83 MHz Data Input and Compu-
tation Rate
K
Four 12 x 12-bit Multipliers with
Individual Data and Coefficient
Inputs
K
Four 256 x 12-bit Coefficient Banks
K
32-bit Accumulator
K
Selectable 16-bit Data Output with
User-Defined Rounding and Limiting
K
Two’s Complement Operands
K
3.3 Volt Power Supply
K
5 Volt Tolerant I/ O
K
120-pin PQFP
FEATURES
DESCRIPTION
DEVICES INCORPORATED
The
LF3347
consists of an array of
four 12 x 12-bit registered multipliers
followed by two summers and a
32-bit accumulator. The LF3347
provides four 256 x 12-bit coefficient
banks which are capable of storing
256 different sets of filter coefficients
for the multiplier array. All multi-
plier data inputs are user accessible
and can be updated every clock cycle
with two’s complement data. The
pipelined architecture has fully
registered input and output ports and
an asynchronous three-state output
enable control to simplify the design
of complex systems.
A 32-bit accumulator allows cumula-
tive word growth which may be
internally rounded to 16-bits. Output
data is updated every clock cycle and
may be held under user control. The
data inputs/ outputs and control
inputs are registered on the rising
edge of CLK. The Control/ Coeffi-
cient Data Input,
CC
11-0
, is registered
on the rising edge of CCCLK.
The LF3347 is ideal for performing
pixel interpolation in image manipu-
lation and filtering applications. The
LF3347 can perform a bilinear inter-
polation of an image (4-pixel kernels)
at real-time video rates when used
LF3347 B
LOCK
D
IAGRAM
D1
11-0
12
12
ENB
1
D2
11-0
12
12
ENB
2
25
D3
11-0
12
12
ENB
3
D4
11-0
12
12
ENB
4
25
S
15-0
ACC
OE
CLK
TO ALL REGISTERS
Coefficient
Bank 1
(256 x 12-bit)
Coefficient
Bank 2
(256 x 12-bit)
Coefficient
Bank 3
(256 x 12-bit)
Coefficient
Bank 4
(256 x 12-bit)
A
7-0
8
ENBA
16
16
CC
11-0
12
LD
Rounding
Selecting
Limiting
Circuit
Rounding/
Limiting
Registers
CCCLK
32
OCEN
4
6
6
NOTE: NUMBERS IN REGISTERS INDICATE
NUMBER OF PIPELINE DELAYS
3
2
2
2
2
SHIFT
4-0
LMTEN
SELLMT
3-0
4
SELRND
3-0
4
5
5
5
4
4
LF
INTERFACE
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